Multi-Gigahertz Nyquist Analog-to-Digital Converters

Table of Contents

1. Frontmatter

2. Chapter 1. Introduction

   Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier

   Abstract

   Analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are the cornerstone of modern electronics due to their fundamental role in virtually any application requiring the transfer of information between the physical (analog) world and the signal processing (digital) world. This introductory chapter starts by outlining the need, applicability, and challenges of data converters in a digital era. Key high-performance ADC applications are briefly discussed, and challenges in simultaneously improving the three main ADC performance parameters are introduced. These come on a circuit level, an architectural level, a system level, and a technology level, with the last one being particularly important as it affects the other three. The main scope of the research is described in this book, and its objectives are also highlighted.

3. Chapter 2. Analog-to-Digital Conversion Fundamentals

   Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier

   Abstract

   This chapter serves as the foundation for the remainder of this book, by covering fundamental A/D conversion principles, some important performance metrics, as well as practical limitations. The two main functions in every A/D conversion, namely sampling and quantization, are reviewed and discussed. The major error sources stemming from the individual blocks of practical converters are identified and analyzed, followed by a review of the most important performance metrics and figures-of-merit. The impact of major error sources on the accuracy-speed-power is derived, leading to the establishment of fundamental limits on a converter’s performance, imposed by circuits, technology, and ultimately physics. These limits form the basis of what may be theoretically achievable and, together with the architectural overheads presented in Chap. 3, serve as guidelines to justify the design choices of the four prototype ICs described in Chaps. 4–7 of this book.

4. Chapter 3. Architectural Considerations for High-Efficiency GHz-Range ADCs

   Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier

   Abstract

   One of the everlasting challenges in the design of data converters is how to get the maximum performance for the minimum amount of energy. To tackle this challenge, this chapter extends the fundamental block-level limits’ derivations of Chap. 2, to an architectural level, in the pursuit of determining the optimal architecture for maximizing the accuracy ⋅ speed ÷ power product. Recent state-of-the-art standings, including major ADC architectures in the foremost conferences, are reviewed and interpreted. A mathematical framework is introduced to estimate and compare the accuracy-speed-power limits of these architectures, with a complete decomposition of the blocks’ contributions. The proposed framework’s power is enhanced with process effects of deep-scaled CMOS nodes, building great insight into architecture and process capabilities.

5. Chapter 4. Ultrahigh-Speed High-Sensitivity Dynamic Comparator

   Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier

   Abstract

   The comparator is an important mixed-signal block, both standalone and within an ADC, where its speed determines to a great extent the ADC sample rate, while its power consumption impacts the overall converter efficiency. This chapter focuses on the design of dynamic regenerative comparators, which is the currently prevailing high-speed low-power choice. After reviewing two widely used comparator circuits, an ultrahigh-speed three-stage fully dynamic comparator is presented. The proposed novel comparator is analyzed and compared against the two prior art circuits by means of derived delay and noise expressions, serving as design guidelines. The experimental verification of the prototype comparator and its prior art, all fabricated in 28 nm CMOS, is presented, along with a recent state-of-the-art comparison.

6. Chapter 5. High-Speed Wide-Bandwidth Single-Channel SAR ADC

   Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier

   Abstract

   The SAR is among the most widely used ADC architectures by virtue of its simple and minimalistic structure, inherently low power consumption, and highly digital nature, allowing it to benefit from technology scaling. Additionally, a number of techniques have emerged to significantly enhance its traditionally low speed. This chapter first reviews the conventional SAR clocking scheme and discusses some noteworthy speed-boosting techniques that have enabled the SAR to be a high-speed protagonist. Then, it introduces the proposed SAR ADC and elaborates on the speed-boosting architectural and circuit principles employed. Finally, the experimental verification of the 28 nm CMOS ADC prototype, including the measurement setup, measured results, and a state-of-the-art comparison, is presented and discussed.

7. Chapter 6. High-Resolution Wide-Bandwidth Time-Interleaved RF ADC

   Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier

   Abstract

   This chapter delves deep into architectural and circuit capabilities to enable high-resolution ADCs (>10-bits) while preserving the multi-GHz sample rate and bandwidth and maximizing the efficiency. Such high resolution, multi-GHz sample rate and bandwidth, low-power RF sampling ADCs are of great interest in next generation wideband communication, data acquisition, and instrumentation applications. First, the needs and challenges for efficiently realizing such RF sampling ADCs are overviewed, and common ADC architectural choices and their trade-offs are briefly discussed. Consequently, a novel TI hybrid RF sampling ADC is presented, and its performance-enabling principles are detailed. Finally, the experimental verification of the ADC prototype in 28 nm CMOS, including the detailed measurement setup, the measured results, and a comparison with recent state-of-the-art, is treated thoroughly.

8. Chapter 7. Ultra-Wideband Direct RF Receiver Analog Front-End

   Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier

   Abstract

   The challenge to continue increasing the RF sampling ADC sample rate and bandwidth, to enable next generation ultra-wideband applications, does not lie only with the converter core. While time-interleaving can enhance the sample rate, the same cannot be said about the bandwidth, which should be extended by the front end preceding the ADC, while maximizing the spectral purity and limiting the excess power consumption. This chapter first revisits the problem of extending the bandwidth beyond several tens of GHz and discusses the major challenges along with a prior art overview. Furthermore, a new ultra-wideband highly integrated analog front end is introduced, and its innovative performance-advancing features are discussed in detail. Finally, the experimental verification of the prototype front end in 16nm FinFET CMOS, including the complete measurement setup, measured results, and a state-of-the-art comparison, is presented and discussed.

9. Chapter 8. Conclusions, Contributions, and Future Work

   Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier

   Abstract

   This closing chapter summarizes the contents of this book, discusses some of its major contributions and their advancing of the data converter field, and finally, proposes future research directions.

10. Backmatter