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Subthreshold Operation of Energy Recovery Circuits Read chapter Read first chapter

2016 | OriginalPaper | Chapter

Multiplexer Based 2’s Complement Circuit for Low Power and High Speed Operation

Authors : Kore Sagar Dattatraya, Belgudri Ritesh Appasaheb, V. S. Kanchana Bhaaskaran

Published in: Microelectronics, Electromagnetics and Telecommunications

Publisher: Springer India

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Abstract

This paper presents a novel multiplexer based 2’s complement circuit that can be used for the subtraction process using 2’s complement method. The proposed multiplexer based 4, 8 and 16-bit 2’s complement circuits are compared with the conventional subtractor circuits using 2’s complement circuits for validating the proposal. Industry Standard EDA Tools and technology libraries have been employed.

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Literature
1.
J.F. Wakerly, Digital Design Principles and Practices, 3rd edn. (Prentice Hall, 2000), p. 47. ISBN 0-13-769191-2
2.
I. Koren, Computer Arithmetic Algorithms. ed. by A.K. Peters (2002). ISBN 1-56881-160-8
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Metadata
Title
Multiplexer Based 2’s Complement Circuit for Low Power and High Speed Operation
Authors
Kore Sagar Dattatraya
Belgudri Ritesh Appasaheb
V. S. Kanchana Bhaaskaran
Copyright Year
2016
Publisher
Springer India
Book
Microelectronics, Electromagnetics and Telecommunications

Print ISBN: 978-81-322-2726-7

Electronic ISBN: 978-81-322-2728-1

Copyright Year: 2016

DOI
https://doi.org/10.1007/978-81-322-2728-1_35