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2013 | OriginalPaper | Chapter

6. NBTI and Its Effect on SRAM

Authors : Jawar Singh, Saraju P. Mohanty, Dhiraj K. Pradhan

Published in: Robust SRAM Designs and Analysis

Publisher: Springer New York

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Abstract

In this chapter, modelling of Negative Bias Temperature Instability (NBTI), how it is incorporated with Static Random Access Memory (SRAM) and its impact on different SRAM cache configurations is presented. Investigations of how NBTI affects different power saving cache strategies employing the standard symmetric and asymmetric 6-transistor (6T) SRAM, and the isolated read-port 6T SRAM bitcells, are presented. It is observed that more than 38–66% of the recovery in stability parameters (SNM and WNM) under different power saving cache strategies have been achieved for different SRAM bitcells based cache configurations. It is also found that the low V_TH transistors age faster than the high V_TH transistors due to NBTI. Hence, NBTI effect is more pronounced in future technologies due to reduction in V_TH with technology scaling. Also NBTI effect is more significant at higher temperature.

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Title: NBTI and Its Effect on SRAM
Authors: Jawar Singh
Saraju P. Mohanty
Dhiraj K. Pradhan
Publisher: Springer New York
Book: Robust SRAM Designs and Analysis
Print ISBN: 978-1-4614-0817-8

Electronic ISBN: 978-1-4614-0818-5

Copyright Year: 2013
DOI: https://doi.org/10.1007/978-1-4614-0818-5_6