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Published in:
2005 | OriginalPaper | Chapter
Network on Chip for Parallel DSP Architectures
Authors : Yuanli Jing, Xiaoya Fan, Deyuan Gao, Jian Hu
Published in: Embedded Software and Systems
Publisher: Springer Berlin Heidelberg
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Network-on-Chip is a new methodology of System-on-Chip design. It can be used to improve communication performance among many computing nodes of parallel DSP architectures. Simulations based on the 16-node 2D-mesh DragonFly DSP architecture show that the routing distance of 72.9% inter-node communication is 1. A fast local router is proposed to improve the performance of this communication. Experiments on our simulator show that overall inter-node communication delay is decreased by 59.4%.