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01-02-2025

Novel junctionless GAA negative capacitance FET based on gate engineering aspects: analytical modeling and performance assessment

Authors: Ibrahim Rahmani, Zohir Dibi, Hichem Farhati, Faycal Djeffal

Published in: Journal of Computational Electronics | Issue 1/2025

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Abstract

We present a new subthreshold analytical model for dual-material junctionless gate-all-around negative capacitance field-effect transistors (DM JL GAA NCFETs). The model accurately reproduces the electrostatic potential distribution, subthreshold current characteristics of the device, threshold voltage, and subthreshold slope. By solving the Landau–Khalatnikov (L–K) equation with Poisson’s equation, the model provides a precise analytical solution that aligns closely with numerical results. The impact of various parameters such as channel length, DM gate ratio, and ferroelectric layer thickness on the device subthreshold behavior is systematically analyzed. It is found that the strategic combination between the JL structure and NC effect can allow achieving enhanced device performance at the nanoscale level. The results demonstrate that the optimized DM JL GAA NCFET exhibits enhanced short-channel performance at nanoscale level, reduced subthreshold swing of 49 mV/dec, lower threshold voltage of 0.20 V, and reduced OFF-current of 1.5 × 10–5 nA. Therefore, the proposed design framework strategy paves the way for designers not only to identify the appropriate DM gate configuration and the suitable ferroelectric material for the development of ultralow-power and high-performance nanoelectronic circuits.

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Metadata
Title
Novel junctionless GAA negative capacitance FET based on gate engineering aspects: analytical modeling and performance assessment
Authors
Ibrahim Rahmani
Zohir Dibi
Hichem Farhati
Faycal Djeffal
Publication date
01-02-2025
Publisher
Springer US
Published in
Journal of Computational Electronics / Issue 1/2025
Print ISSN: 1569-8025
Electronic ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-024-02241-x