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2020 | OriginalPaper | Chapter

6. On-Chip Ageing Monitoring and System Adaptation

Authors : Lorena Anghel, Florian Cacho, Riddhi Jitendrakumar Shah

Published in: Ageing of Integrated Circuits

Publisher: Springer International Publishing

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Abstract

Process, voltage, temperature and ageing variations have become important issues in nanometre technology nodes, and thus on-chip accurate reliability and performance monitors have become necessary for adaptive compensation schemes. This chapter presents up-to-date state-of-the-art performance and reliability monitors, insertion methodology and experimental results of different monitors used for process and environment variations as well as ageing compensation. Voltage and frequency scaling techniques are combined with monitors to ensure fault-free operation. Measurements and simulations were performed on large sample sets for varied range of process, voltages, temperatures and ageing to argument on the choice of paths to be monitored and to illustrate adaptive compensation techniques.

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Literature
2.
go back to reference Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC). (2015, September). Rebooting the IT revolution: A call to action. Technical report. Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC). (2015, September). Rebooting the IT revolution: A call to action. Technical report.
4.
go back to reference Huard, V. et al. (2014). Adaptative wear out management with in-situ management In: International reliability physics symposium (IRPS 2014) (pp. 6B.4.1–6B.4.11). Huard, V. et al. (2014). Adaptative wear out management with in-situ management In: International reliability physics symposium (IRPS 2014) (pp. 6B.4.1–6B.4.11).
5.
go back to reference Anghel, L., Benhassain, A., & Sivadasan, A. (2016, April 25–27). Early system failure prediction by using ageing in situ monitors: Methodology of implementation and application results. IEEE 34th VLSI test symposium (VTS’16), Las Vegas, NE, doi: https://doi.org/10.1109/VTS.2016.7477316 Anghel, L., Benhassain, A., & Sivadasan, A. (2016, April 25–27). Early system failure prediction by using ageing in situ monitors: Methodology of implementation and application results. IEEE 34th VLSI test symposium (VTS’16), Las Vegas, NE, doi: https://​doi.​org/​10.​1109/​VTS.​2016.​7477316
7.
go back to reference Cacho, F., Benhassain, A., Shah, R., Mhira, S., Huard, V., & Anghel, L. (2017). Investigation of critical path selection for in-situ monitors insertion.In: IEEE international on line testing symposium. Cacho, F., Benhassain, A., Shah, R., Mhira, S., Huard, V., & Anghel, L. (2017). Investigation of critical path selection for in-situ monitors insertion.In: IEEE international on line testing symposium.
8.
go back to reference Garros, X., Besson, P., Reimbold, G., Loup, V., Salvetat, T., Rochat, N., Lhostis, S., & Boulanger, F. (2008). Impact of crystallinity of high-k oxides on vt instabilities of nmos devices assessed by physical and electrical measurements. IEEE international reliability physics symposium, https://doi.org/10.1109/RELPHY.2008.4558907. Garros, X., Besson, P., Reimbold, G., Loup, V., Salvetat, T., Rochat, N., Lhostis, S., & Boulanger, F. (2008). Impact of crystallinity of high-k oxides on vt instabilities of nmos devices assessed by physical and electrical measurements. IEEE international reliability physics symposium, https://​doi.​org/​10.​1109/​RELPHY.​2008.​4558907.
9.
go back to reference Bhardwaj, S., Wang, W., Vattikonda, R., Cao, Y., & Vrudhula, V. S. (2006). Predictive modeling of the nbti effect for reliable design. In: Custom integrated circuits conference, 2006. CICC’06. IEEE (pp. 189–192). IEEE. Bhardwaj, S., Wang, W., Vattikonda, R., Cao, Y., & Vrudhula, V. S. (2006). Predictive modeling of the nbti effect for reliable design. In: Custom integrated circuits conference, 2006. CICC’06. IEEE (pp. 189–192). IEEE.
10.
go back to reference Naphade, T., Goel N., Nair, P. R., & Mahapatra, S. (2013). Investigation of stochastic implementation of reaction diffusion (RD) models for nbti related interface trap generation. In: Reliability physics symposium (IRPS 2013), 2013 IEEE international (p. XT–5). IEEE. Naphade, T., Goel N., Nair, P. R., & Mahapatra, S. (2013). Investigation of stochastic implementation of reaction diffusion (RD) models for nbti related interface trap generation. In: Reliability physics symposium (IRPS 2013), 2013 IEEE international (p. XT–5). IEEE.
11.
go back to reference Denais, M., Parthasarathy, C., Ribes, G., Rey-Tauriac, Y., Revil, N., Bravaix A., Huard, V., & Perrier, F. (2004, December). On-the- characterization of NBTI in ultra-thin gate oxide pmosfet’s. In: Electron devices meeting, 2004. IEDM technical digest. IEEE international (pp. 109–112). Denais, M., Parthasarathy, C., Ribes, G., Rey-Tauriac, Y., Revil, N., Bravaix A., Huard, V., & Perrier, F. (2004, December). On-the- characterization of NBTI in ultra-thin gate oxide pmosfet’s. In: Electron devices meeting, 2004. IEDM technical digest. IEEE international (pp. 109–112).
12.
go back to reference Huard, V., Parthasarathy, C., Guerin, C., Valentin, T., Pion, E., Mammasse, M., Planes, N., & Amus, L. C. (2008). Nbti degradation: From transistor to sram arrays. In Reliability physics symposium, 2008. IRPS 2008. IEEE international (pp. 289–300). IEEE. Huard, V., Parthasarathy, C., Guerin, C., Valentin, T., Pion, E., Mammasse, M., Planes, N., & Amus, L. C. (2008). Nbti degradation: From transistor to sram arrays. In Reliability physics symposium, 2008. IRPS 2008. IEEE international (pp. 289–300). IEEE.
13.
go back to reference Kaczer, B., Grasser, T., Roussel, P. J., Franco, J., Degraeve, R., Ragnarsson, L-A., Simoen, E., Groeseneken, G., & Reisinger, H. (2010). Origin of nbti variability in deeply scaled pfets. In Reliability physics symposium (IRPS), 2010 IEEE international (pp. 26–32). IEEE. Kaczer, B., Grasser, T., Roussel, P. J., Franco, J., Degraeve, R., Ragnarsson, L-A., Simoen, E., Groeseneken, G., & Reisinger, H. (2010). Origin of nbti variability in deeply scaled pfets. In Reliability physics symposium (IRPS), 2010 IEEE international (pp. 26–32). IEEE.
14.
go back to reference Cacho, F., Piriou, E., Heron, O., & Huard, V. (2015). Simulation framework for optimizing SRAM power consumption under reliability constraint, median workshop. Cacho, F., Piriou, E., Heron, O., & Huard, V. (2015). Simulation framework for optimizing SRAM power consumption under reliability constraint, median workshop.
15.
go back to reference Reddy, V., Carulli, J. M., Krishnan, A. T., Bosch, W., & Burgess, B. (2004). Impact of negative bias temperature instability on product parametric drift. In International test conference (ITC) (pp. 148–155). Citeseer. Reddy, V., Carulli, J. M., Krishnan, A. T., Bosch, W., & Burgess, B. (2004). Impact of negative bias temperature instability on product parametric drift. In International test conference (ITC) (pp. 148–155). Citeseer.
16.
go back to reference Weckx, P., Kaczer, B., Toledano-Luque, M., Grasser, T., Roussel, P., Kukner, H., Raghavan, P., Catthoor, F., & Groeseneken, G. (2013) Defect-based methodology for workload-dependent circuit lifetime projections-application to sram. In: Reliability physics symposium (IRPS), 2013 IEEE international (pp. 3A–4). IEEE. Weckx, P., Kaczer, B., Toledano-Luque, M., Grasser, T., Roussel, P., Kukner, H., Raghavan, P., Catthoor, F., & Groeseneken, G. (2013) Defect-based methodology for workload-dependent circuit lifetime projections-application to sram. In: Reliability physics symposium (IRPS), 2013 IEEE international (pp. 3A–4). IEEE.
17.
go back to reference Chen, K.-L., Saller, S. A., Groves, I. A., & Scott, D. B. (1985). Reliability effects on mos transistors due to hot-carrier injection. Solid-State Circuits, IEEE Journal of, 20(1), 306–313.CrossRef Chen, K.-L., Saller, S. A., Groves, I. A., & Scott, D. B. (1985). Reliability effects on mos transistors due to hot-carrier injection. Solid-State Circuits, IEEE Journal of, 20(1), 306–313.CrossRef
18.
go back to reference Cacho, F., Mora, P., Arfaoui, W., Federspiel, X., & Huard, V. (2014). HCI/BTI coupled model: the path for accurate and predictive reliability simulations. In: Reliability physics symposium, 2014 IEEE international (pp. 5D–4). IEEE. Cacho, F., Mora, P., Arfaoui, W., Federspiel, X., & Huard, V. (2014). HCI/BTI coupled model: the path for accurate and predictive reliability simulations. In: Reliability physics symposium, 2014 IEEE international (pp. 5D–4). IEEE.
20.
go back to reference Burd, T. D., Pering, T. A., Stratakos, A. J., & Brodersen, R. W. (2000). A dynamic voltage scaled microprocessor system. IEEE Journal of Solid-State Circuits, 35(11), 1571–1580.CrossRef Burd, T. D., Pering, T. A., Stratakos, A. J., & Brodersen, R. W. (2000). A dynamic voltage scaled microprocessor system. IEEE Journal of Solid-State Circuits, 35(11), 1571–1580.CrossRef
21.
go back to reference Kuroda, T., Suzuki, K., Mita, S., Fujita, T., Yamane, F., Sano, F., Chiba, A., Watanabe, Y., & Matsuda, K. (1998). Takeo Maeda, and others. Variable supply-voltage scheme for low-power high-speed CMOS digital design. IEEE Journal of Solid-State Circuits, 33(3), 454–462.CrossRef Kuroda, T., Suzuki, K., Mita, S., Fujita, T., Yamane, F., Sano, F., Chiba, A., Watanabe, Y., & Matsuda, K. (1998). Takeo Maeda, and others. Variable supply-voltage scheme for low-power high-speed CMOS digital design. IEEE Journal of Solid-State Circuits, 33(3), 454–462.CrossRef
22.
go back to reference Cho, M., Kim, S. T., Tokunaga, C., Augustine, C., Kulkarni, J. P., Ravichandran, K., Tschanz, J. W., Khellah, M. M., & De, V. (2017). Postsilicon voltage guard-band reduction in a 22 nm graphics execution core using adaptive voltage scaling and dynamic power gating. IEEE Journal of Solid-State Circuits, 52, 50.CrossRef Cho, M., Kim, S. T., Tokunaga, C., Augustine, C., Kulkarni, J. P., Ravichandran, K., Tschanz, J. W., Khellah, M. M., & De, V. (2017). Postsilicon voltage guard-band reduction in a 22 nm graphics execution core using adaptive voltage scaling and dynamic power gating. IEEE Journal of Solid-State Circuits, 52, 50.CrossRef
23.
go back to reference Ernst, D., Kim, N. S., Das, S., Pant, S., Rao, R., Pham, T., Ziesler, C., Blaauw, D., Austin, T., Flautner, K., & Mudge, T. (2003). Razor: a low-power pipeline based on circuit-level timing speculation. In: Proceedings 36th annual IEEE/ACM international symposium on microarchitecture. MICRO-36. Ernst, D., Kim, N. S., Das, S., Pant, S., Rao, R., Pham, T., Ziesler, C., Blaauw, D., Austin, T., Flautner, K., & Mudge, T. (2003). Razor: a low-power pipeline based on circuit-level timing speculation. In: Proceedings 36th annual IEEE/ACM international symposium on microarchitecture. MICRO-36.
24.
go back to reference Das, S., Tokunaga, C., Pant, S., Ma, W.-H., Kalaiselvan, S., Lai, K., Bull, D. M., & Blaauw, D. T. (2009). RazorII: In situ error detection and correction for PVT and SER tolerance. IEEE Journal of Solid-State Circuits, 44(1), 32–48.CrossRef Das, S., Tokunaga, C., Pant, S., Ma, W.-H., Kalaiselvan, S., Lai, K., Bull, D. M., & Blaauw, D. T. (2009). RazorII: In situ error detection and correction for PVT and SER tolerance. IEEE Journal of Solid-State Circuits, 44(1), 32–48.CrossRef
25.
go back to reference Bowman, K. A., Tschanz, J. W., Kim, N. S., Lee, J. C., Wilkerson, C. B., Lu, S. L., Karnik, T., & De, V. K. (2008). Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance. In: 2008 IEEE international conference on integrated circuit design and technology and tutorial. Bowman, K. A., Tschanz, J. W., Kim, N. S., Lee, J. C., Wilkerson, C. B., Lu, S. L., Karnik, T., & De, V. K. (2008). Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance. In: 2008 IEEE international conference on integrated circuit design and technology and tutorial.
26.
go back to reference Shah, R. et al. (2018). Ageing investigation of digital circuits using in-situ monitor. In Proceedings of 2018 IEEE international reliability workshop, Stanford sierra conference center, Fallen Leaf Lake, CA, USA. Shah, R. et al. (2018). Ageing investigation of digital circuits using in-situ monitor. In Proceedings of 2018 IEEE international reliability workshop, Stanford sierra conference center, Fallen Leaf Lake, CA, USA.
27.
go back to reference Nicolaidis, M.. (1999, Apr). Time redundancy based soft-error tolerant circuits to rescue very deep submicron. In: Proceedings of 17th IEEE VLSI test symposium (pp. 86–94), Dana Point, CA. Nicolaidis, M.. (1999, Apr). Time redundancy based soft-error tolerant circuits to rescue very deep submicron. In: Proceedings of 17th IEEE VLSI test symposium (pp. 86–94), Dana Point, CA.
28.
go back to reference Keane, J., Wang, X., Persaud, D., & Kim, C. H. (2010). An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB. IEEE Journal of Solid-State Circuits, 45(4), 817–829.CrossRef Keane, J., Wang, X., Persaud, D., & Kim, C. H. (2010). An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB. IEEE Journal of Solid-State Circuits, 45(4), 817–829.CrossRef
29.
go back to reference Kim, T. T. H., Lu, P. F., Jenkins, K. A., & Kim, C. H. (2015). A ring-oscillator-based reliability monitor for isolated measurement of NBTI and PBTI in high-k/metal gate technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23, 1360–1364.CrossRef Kim, T. T. H., Lu, P. F., Jenkins, K. A., & Kim, C. H. (2015). A ring-oscillator-based reliability monitor for isolated measurement of NBTI and PBTI in high-k/metal gate technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23, 1360–1364.CrossRef
30.
go back to reference Zhao, Y., & Kerkhoff, H. G. (2016). Highly dependable multi-processor SoCs employing lifetime prediction based on health monitors. In: 2016 IEEE 25th Asian test symposium (ATS). Zhao, Y., & Kerkhoff, H. G. (2016). Highly dependable multi-processor SoCs employing lifetime prediction based on health monitors. In: 2016 IEEE 25th Asian test symposium (ATS).
31.
go back to reference Harada, R., Mitsuyama, Y., Hashimoto, M., & Onoye, T. (2010). Measurement circuits for acquiring SET pulse width distribution with sub-FO1- inverter-delay resolution. In: 11th international symposium on quality electronic design (ISQED). ISQED. Harada, R., Mitsuyama, Y., Hashimoto, M., & Onoye, T. (2010). Measurement circuits for acquiring SET pulse width distribution with sub-FO1- inverter-delay resolution. In: 11th international symposium on quality electronic design (ISQED). ISQED.
32.
go back to reference Wang, W. et al. (2007, Nov). An efficient method to identify critical gates under circuit ageing. In: Proceedings of ICCAD (pp. 735–740). Wang, W. et al. (2007, Nov). An efficient method to identify critical gates under circuit ageing. In: Proceedings of ICCAD (pp. 735–740).
33.
go back to reference Benhassain, A., Mhira, S., Cacho, F., Huard, V., & Anghel, L. (2016). In-situ slack monitors: taking up the challenge of on-die monitoring of variability and reliability.In: 2016 1st IEEE international verification and security workshop (IVSW). Benhassain, A., Mhira, S., Cacho, F., Huard, V., & Anghel, L. (2016). In-situ slack monitors: taking up the challenge of on-die monitoring of variability and reliability.In: 2016 1st IEEE international verification and security workshop (IVSW).
34.
go back to reference Sivadasan, A., Cacho, F., Benhassain, S. A., Huard, V., & Anghel, L. (2016). Study of workload impact on BTI HCI induced ageing of digital circuits. In: Proceedings of the 2016 conference on design, automation & test in Europe, San Jose, CA. Sivadasan, A., Cacho, F., Benhassain, S. A., Huard, V., & Anghel, L. (2016). Study of workload impact on BTI HCI induced ageing of digital circuits. In: Proceedings of the 2016 conference on design, automation & test in Europe, San Jose, CA.
35.
go back to reference Portolan, M. (2016). A novel test generation and application flow for functional access to IEEE 1687 instruments. In: 2016 21th IEEE European test symposium (ETS). Portolan, M. (2016). A novel test generation and application flow for functional access to IEEE 1687 instruments. In: 2016 21th IEEE European test symposium (ETS).
36.
go back to reference Von Kaenel, V., Macken, P., & Degrauwe, M. G. R. (October 1990). A voltage reduction technique for battery-operated systems. IEEE Journal of Solid-State Circuits, 25(5), 1136–1140.CrossRef Von Kaenel, V., Macken, P., & Degrauwe, M. G. R. (October 1990). A voltage reduction technique for battery-operated systems. IEEE Journal of Solid-State Circuits, 25(5), 1136–1140.CrossRef
37.
go back to reference Niessen, C., & Van, B. C. H. (1993, June). An apparatus featuring a feedback signal for controlling a powering voltage for asynchronous electronic circuitry therein. European Patent Office, EP0549052B1. Niessen, C., & Van, B. C. H. (1993, June). An apparatus featuring a feedback signal for controlling a powering voltage for asynchronous electronic circuitry therein. European Patent Office, EP0549052B1.
38.
go back to reference Nielsen, L. S., Niessen, C., Sparso, J., & Van Berkel, K. (1994). Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(4), 391–397.CrossRef Nielsen, L. S., Niessen, C., Sparso, J., & Van Berkel, K. (1994). Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(4), 391–397.CrossRef
39.
go back to reference Calhoun, B. H., & Chandrakasan, A. P. (January 2006). Ultra-Dynamic Voltage Scaling (UDVS) using sub-threshold operation and local voltage dithering. IEEE Journal of Solid-State Circuits, 41(1), 238–245.CrossRef Calhoun, B. H., & Chandrakasan, A. P. (January 2006). Ultra-Dynamic Voltage Scaling (UDVS) using sub-threshold operation and local voltage dithering. IEEE Journal of Solid-State Circuits, 41(1), 238–245.CrossRef
40.
go back to reference Miro-Panades, I., Beigne, E., Thonnart, Y., Alacoque, L., Vivet, P., Lesecq, S., Puschini, D., Molnos, A., Thabet, F., Tain, B., Chehida, K. B., Engels, S., Wilson, R., & Fuin, D. (July 2014). A fine-grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32 nm GALS MPSoC. IEEE Journal of Solid-State Circuits, 49(7), 1475–1486.CrossRef Miro-Panades, I., Beigne, E., Thonnart, Y., Alacoque, L., Vivet, P., Lesecq, S., Puschini, D., Molnos, A., Thabet, F., Tain, B., Chehida, K. B., Engels, S., Wilson, R., & Fuin, D. (July 2014). A fine-grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32 nm GALS MPSoC. IEEE Journal of Solid-State Circuits, 49(7), 1475–1486.CrossRef
41.
go back to reference Albea, C., Puschini, D., Lesecq, S., & Beigné, E. (2011). Optimal and robust control for a small-area FLL. In: Control & automation (MED), 2011 19th mediterranean conference on (pp. 1100–1105). IEEE. Albea, C., Puschini, D., Lesecq, S., & Beigné, E. (2011). Optimal and robust control for a small-area FLL. In: Control & automation (MED), 2011 19th mediterranean conference on (pp. 1100–1105). IEEE.
42.
go back to reference Benhassain, A., Cacho, F., Huard, V., Saliva, M., Anghel, L., Parthasarathy, C., Jain, A., & Giner, F. (2015). Timing in-situ monitors: Implementation strategy and applications results. In: 2015 IEEE custom integrated circuits conference (CICC). Benhassain, A., Cacho, F., Huard, V., Saliva, M., Anghel, L., Parthasarathy, C., Jain, A., & Giner, F. (2015). Timing in-situ monitors: Implementation strategy and applications results. In: 2015 IEEE custom integrated circuits conference (CICC).
Metadata
Title
On-Chip Ageing Monitoring and System Adaptation
Authors
Lorena Anghel
Florian Cacho
Riddhi Jitendrakumar Shah
Copyright Year
2020
DOI
https://doi.org/10.1007/978-3-030-23781-3_6