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Improving the Performance of Adaptive Cache in Reconfigurable VLIW Processor Read chapter Read first chapter

2017 | OriginalPaper | Chapter

Parameter Sensitivity in Virtual FPGA Architectures

Authors : Peter Figuli, Weiqiao Ding, Shalina Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker

Published in: Applied Reconfigurable Computing

Publisher: Springer International Publishing

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Abstract

Virtual FPGAs add the benefits of increased flexibility and application portability on bitstream level across any underlying commercial off-the-shelf FPGAs at the expense of additional area and delay overhead. Hence it becomes a priority to tune the architecture parameters of the virtual layer. Thereby, the adoption of parameter recommendations intended for physical FPGAs can be misleading, as they are based on transistor level models. This paper presents an extensive study of architectural parameters and their effects on area and performance by introducing an extended parameterizable virtual FPGA architecture and deriving suitable area and delay models. Furthermore, a design space exploration methodology based on these models is carried out. An analysis of over 1400 benchmark-runs with various combinations of cluster and LUT size reveals high parameter sensitivity with variances up to \(\pm 95.9\%\) in area and \(\pm 78.1\%\) in performance and a discrepancy to the studies on physical FPGAs.

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Literature
1.
2.
3.
Ahmed, E., Rose, J.: The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12(3), 288–298 (2004)CrossRef
4.
Betz, V., Rose, J.: Cluster-based logic blocks for FPGAs: area-efficiency vs. input sharing and size. In: Custom Integrated Circuits Conference, Proceedings of the IEEE 1997, pp. 551–554 (1997)
5.
Brant, A., Lemieux, G.G.F.: ZUMA: an open FPGA overlay architecture. In: Field-Programmable Custom Computing Machines (FCCM), April 2012
6.
Figuli, P., Huebner, M., et al.: A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime core fusion. In: NASA/ESA 6th Conference on Adaptive Hardware and Systems (AHS 2011), June 2011
7.
Gao, H., Yang, Y., Ma, X., Dong, G.: Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations. In: Sixth International Symposium on Quality Electronic Design (ISQED 2005), pp. 370–374, March 2005
8.
Gupta, P.K.: Accelerating datacenter workloads. In: 26th International Conference on Field Programmable Logic and Applications (FPL), August 2016
9.
Huebner, M., Figuli, P., Girardey, R., Soudris, D., Siozos, K., Becker, J.: A heterogeneous multicore system on chip with run-time reconfigurable virtual FPGA architecture. In: 18th Reconfigurable Architectures Workshop, May 2011
10.
Lagadec, L., Lavenier, D., Fabiani, E., Pottier, B.: Placing, routing, and editing virtual FPGAs. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 357–366. Springer, Heidelberg (2001). doi:10.​1007/​3-540-44687-7_​37 CrossRef
11.
Luu, J., Goeders, J., et al.: VTR 7.0: next generation architecture and CAD system for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7(2), 6:1–6:30 (2014)CrossRef
12.
Lysecky, R., Miller, K., Vahid, F., Vissers, K.: Firm-core virtual FPGA for just-in-time FPGA compilation. In: Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-programmable Gate Arrays, p. 271 (2005)
13.
Putnam, A.: Large-scale reconfigurable computing in a Microsoft datacenter. In: Proceedings of the 26th IEEE Symposium on High-Performance Chips (2014)
14.
Rose, J., Francis, R.J., Lewis, D., Chow, P.: Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency. IEEE J. Solid-State Circ. 25(5), 1217–1225 (1990)CrossRef
15.
Tang, X., Wang, L.: The effect of LUT size on nanometer FPGA architecture. In: 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1–4, October 2012
Metadata
Title
Parameter Sensitivity in Virtual FPGA Architectures
Authors
Peter Figuli
Weiqiao Ding
Shalina Figuli
Kostas Siozios
Dimitrios Soudris
Jürgen Becker
Copyright Year
2017
Book
Applied Reconfigurable Computing

Print ISBN: 978-3-319-56257-5

Electronic ISBN: 978-3-319-56258-2

Copyright Year: 2017

DOI
https://doi.org/10.1007/978-3-319-56258-2_13