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2018 | OriginalPaper | Chapter

1. Patent Issues of Fan-Out Wafer-Level Packaging

Author : John H. Lau

Published in: Fan-Out Wafer-Level Packaging

Publisher: Springer Singapore

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Abstract

In the industry, research institute, and university, there are many engineers, researchers, students, and professors working on fan-out wafer-level packaging. In order to avoid the granted patents in this area, they are trying various methods such as die-up, die-down, die-first, die-last, RDL (redistribution layer)-first, RDL-last, mold-first, mold-last, round temporary carrier, and rectangular temporary carrier. In this chapter, the patent issues of fan-out wafer/panel-level packaging will be investigated. Emphasis will be placed on the claims of the granted patents and the range of things which might be covered under the patents. Depending on the RDL line width/spacing, the material, process, equipment, and application of fan-out wafer/panel-level packaging are examined and some recommendations are made. The patents which impacting the semiconductor packaging the most, so far, will be briefly mentioned first.

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next chapter Flip Chip Technology Versus FOWLP

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Title: Patent Issues of Fan-Out Wafer-Level Packaging
Author: John H. Lau
Publisher: Springer Singapore
Book: Fan-Out Wafer-Level Packaging
Print ISBN: 978-981-10-8883-4

Electronic ISBN: 978-981-10-8884-1

Copyright Year: 2018
DOI: https://doi.org/10.1007/978-981-10-8884-1_1