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2019 | OriginalPaper | Chapter

Performance Evaluation of Multi-operands Floating-Point Adder

Authors : Arvind Kumar, Sunil Kumar, Prateek Raj Gautam, Akshay Verma, Tarique Rashid

Published in: Recent Trends in Communication, Computing, and Electronics

Publisher: Springer Singapore

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Abstract

In this paper, an architecture is presented for a fused floating-point three operand adder unit. This adder executes two additions within a single unit. The purpose of this execution is to lessen total delay, die area, and power consumption in contrast with traditional addition method. Various optimization techniques including exponent comparison, alignment of significands, leading zero detection, addition, and rounding are used to diminish total delay, die area, and power consumption. In addition to this, the comparison is described of different blocks in term for die area, total delay, and power consumption. The proposed scheme is designed and implemented on Xilinx ISE Design 14.7 and synthesized on Synopsis.

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previous chapter Level-Wise Scheduling Algorithm for Linearly Extensible Multiprocessor Systems
next chapter An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full Adder
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Metadata
Title
Performance Evaluation of Multi-operands Floating-Point Adder
Authors
Arvind Kumar
Sunil Kumar
Prateek Raj Gautam
Akshay Verma
Tarique Rashid
Copyright Year
2019
Publisher
Springer Singapore
Book
Recent Trends in Communication, Computing, and Electronics

Print ISBN: 978-981-13-2684-4

Electronic ISBN: 978-981-13-2685-1

Copyright Year: 2019

DOI
https://doi.org/10.1007/978-981-13-2685-1_51