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2018 | OriginalPaper | Chapter

Power Aware Network on Chip Test Scheduling with Variable Test Clock Frequency

Authors : Harikrishna Parmar, Usha Mehta

Published in: Ubiquitous Communications and Network Computing

Publisher: Springer International Publishing

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Abstract

For a stated core, the test time changes in a staircase pattern with the width of Test Access Mechanism (TAM). The core test time cannot decrease all time with increase in TAM width. However, the test time can always be diminished with increasing the test clock speed but clock speed cannot be increased beyond power limits. Here, a new method is proposed to reduce the Network on Chip (NoC) test time, by differing the test clock frequency such that it doesn’t cross the predefined power limit. The power dissipation, test clock frequency and overall test time is the three trade off. In the proposed method, the clock frequency is optimized to minimize the total test application time (TAT) considering the power limits. Experimental results show an reduction of 48% over existing solution for the benchmark system on chip (SoC) D695, P93791 and P22810.

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previous chapter Dimensional Modification Induced Band Gap Tuning in 2D-Photonic Crystal for Advanced Communication and Other Application

Moreno, E., Webber, T., Marcon, C., Moraes, F., Calazans, N.: NoC: a monitored network on chip with path adaptation mechanism. Syst. Archit. 60, 783–795 (2014)CrossRef

Ansari, A., Song, J., Kim, M., Park, S.: Parallel test method for NoC-based SoCs. In: Proceedings IEEE International SoC Design Conference (ISOCC), pp. 116–119 (2009)

Touzene, A.: On all-to-all broadcast in dense Gaussian network on-chip. IEEE Trans. Parallel Distrib. Syst. 26, 1085–1095 (2015)CrossRef

Cota, E.: The impact of NoC reuse on the testing of core-based systems. In: Proceedings of the IEEE VLSI Test Symp, pp. 128–133 (2003)

Larsson, E.: Introduction to Advanced System-on-Chip Test Design and Optimization. Springer, Heidelberg (2005). https://doi.org/10.1007/b135763

Iyengar, V., Chakrabarty, K., Marinissen, E.: Test wrapper and test access mechanism co-optimization for system-on-chip. J. Electron. Test. Theory Appl. 18, 213–230 (2002)CrossRef

Iyengar, V., Chakrabarty, K., Marinissen, E.J.: On using rectangle packing for SOC wrapper/TAM co-optimization. In: Proceedings of the 20th IEEE VLSI Test Symposium (2002)

Zhao, D., Upadhyaya, S.: Power constrained test scheduling with dynamically varied TAM. In: Proceedings of the 21st IEEE VLSI Test Symposium (2003)

Larsson, E., Fujiwara, H.: Power constrained preemptive TAM scheduling. In: Proceedings of the Seventh IEEE European Test Workshop (2002)

10.

Cota, E., Carro, L., Lubaszewski, M.: Reusing an on-chip network for the test of core-based systems. ACM Trans. Des. Autom. Electron. Syst. 9, 471–499 (2004)CrossRef

11.

Cota, E., Liu, C.: Constraint-driven test scheduling for NoC based systems. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 25, 2465–2478 (2006)CrossRef

12.

Amory, A., Lazzari, C., Lubaszewski, S., Moraes, S.: A new test scheduling algorithm based on networks-on-chip as test access mechanisms. J. Parallel Distrib. Comput. 71, 675–686 (2011)CrossRef

13.

Chakrabarty, K.: Test scheduling for core based systems using mixed-integer linear programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19, 1163–1174 (2000)CrossRef

14.

Chattopadhyay, S., Reddy, K.: Genetic algorithm based test scheduling and test access mechanism design for system-on-chips. In: Proceedings of the 16th International Conference on VLSI Design, pp. 341–346 (2003)

15.

Iyengar, V., Chakrabarty, K.: System on-a-chip test scheduling with precedence relationships, preemption, and power constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21, 1088–1094 (2002)CrossRef

16.

Liu, C., Iyengar, V.: Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking. In: Proceedings Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 650–655 (2006)

17.

Liu, C., Shi, J., Cota, E., Iyengar, V.: Power-aware test scheduling in network-on-chip using variable-rate on-chip clocking. In: Proceedings of the 23rd IEEE VLSI Test Symposium (VTS), pp. 349–354 (2005)

18.

Nolen, M., Mahapatra, R.: TDM test scheduling method for network-on-chip systems. In: Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV), pp. 90–98 (2005)

19.

Su, C., Wu, C.: A graph-based approach to power-constrained SOC test scheduling. J. Electron. Test. Theory Appl. 20, 45–60 (2004)CrossRef

20.

Zou, W., Reddy, M., Pomeranz, I., Huang, Y.: SOC test scheduling using simulated annealing. In: Proceedings of the 21st IEEE VLSI Test Symposium (VTS), pp. 325–330 (2003)

21.

Ahn, J., Sungho, K.: Test scheduling of NoC-based SoCs using multiple test clocks. ETRI J. 28, 475–485 (2006)CrossRef

22.

Xiang, D., Zhang, Y.: Cost-effective power-aware core testing in NoCs based on a New unicast-based multicast scheme. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30, 135–147 (2011)CrossRef

23.

Aktouf, A.: Complete strategy for testing an on-chip multiprocessor architecture. IEEE Des. Test Comput. 19, 18–28 (2002)CrossRef

24.

Richter, M., Chakrabarty, K.: Optimization of test pin- count, test scheduling, and test access for NoC-based multicore SoCs. IEEE Trans. Comput. 63, 691–702 (2014)MathSciNetCrossRefMATH

25.

Agrawal, M., Richter, M., Chakrabarty, K.: Test-delivery optimization in manycore SOC. IEEE Trans. Comput.-Aided Des. Integr. Circuits. Syst. 33(7) (2014)

26.

Ansari, A., Kim, D., Jung, J., Park, S.: Hybrid test data transportation scheme for advanced NoC-based SoCs. J. Semicond. Technol. Sci. 15, 85–95 (2015)CrossRef

27.

Marinissen, E., Iyengar, V., Chakrabarty, K.: A set of benchmarks for modular testing of SOCs. In: Proceedings International Test Conference (ITC), pp. 519–528 (2002)

28.

Pouget, J., Larsson, E., Peng, Z.: SOC test time minimization under multiple constraints. In: Proceedings of the 12th Asian Test Symposium (ATS), pp. 312–317 (2003)

29.

Hu, C., Li, Z., Lu, C., Jia, M.: Test scheduling for network-on-chip using XY-direction connected subgraph partition and multiple test clocks. J. Electron. Test. 32, 31–42 (2016)CrossRef

Title: Power Aware Network on Chip Test Scheduling with Variable Test Clock Frequency
Authors: Harikrishna Parmar
Usha Mehta
Publisher: Springer International Publishing
Book: Ubiquitous Communications and Network Computing
Print ISBN: 978-3-319-73422-4

Electronic ISBN: 978-3-319-73423-1

Copyright Year: 2018
DOI: https://doi.org/10.1007/978-3-319-73423-1_23

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