Power Consumption in Cellular Automata

Cellular Automata (CAs) have been established as one of the most intriguing and efficient computational tools of our era with unique properties to fit well with the most of the upcoming nanotechnological and parallel computation aspects. Algorithms based on CAs are ideally suited for hardware implementation, due to their discreteness and their simple, regular and modular structure with local interconnections. On the other hand, power dissipation is considered as a rather limiting parameter for the advancement of high performance hardware design. In this chapter the undergoing relationship between CAs and the corresponding power consumption would be exploited as a matter of importance for their hardware design analysis with many promising aspects. First of all in order to establish a clear connection, a power estimation model for combinational logic circuits using CA and focused on glitching estimation will be presented to elucidate the application of CA model to hardware power dissipation measurements. Following that, the power consumption of CA based logic circuits and namely of 1-d CAs rules logic circuits will be analytically investigated. In particular, CMOS power consumption estimation measurements for all the Wolfram 1-d CAs rules as well as entropy variation measurements were conducted for various study cases and different initial conditions and the findings are discussed in detail and in terms of 1-d CAs rules categorization.