Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013)

The creation and consumption of data is exponentially increasing, driven by everything from networked mobile devices to consumer apps to big data in enterprise organizations. The trends toward more cloud-based computing and centralized hosting are, in turn, triggering an unprecedented migration and consolidation of data into large-scale data centers.

The proliferation of internet of things beating human population, trending needs of aging population demanding service on demand, easy access to scalable servers and clouds of services anytime anywhere wide range of marketing is driving the home to SMART HOME which will soon be a reality. This paper presents the technologies responsible for this transformation.

Today, there are two distinct branches for the design of System on Chips (SoC’s) and Embedded Systems. Yet, at the advent of systems that will do everything, all the time, everywhere the notions of SoC and embedded systems design need to grow and expand to encompass all of a system’s computational and physical elements. Often referred to as cyber-physical systems (CPS) when these two are combined, it is at the heart of design of the emerging smart energy grids, automotive domain, healthcare, entertainment, consumer applications, and more. The economic and societal potential is greater than that we have already witnessed with mobile consumer devices. The seeds of support for CPS will enable machine-to-machine systems, the Internet of Things, and more. What impact will this have on design? What might the EDA tools to design cyber-physical systems look like? And when will this happen?

This paper captures new trends in semiconductor technology, and how it influences and enables the design of future systems, and to the creation of “smart” devices. The paper also explains some of the smart electronics trends in mems, imagers, biomedical applications and illustrates the collaborative model of imec to achieve make this possible.

The talk will address how the computing and communications world has changed as the Internet migrates to its next phase. The new applications like social networking, advanced search engines, and PDA applications have integrated and evolved the telecom, video transmission, and data networks into a single entity. The need for searching any kind of information and quickly providing to customers is becoming the competitive advantage to service providers. This has made the networks migrate to storage, cloud, access, and delivery model. The new standards and SoCs based on that will continue to evolve and create opportunities to develop new technologies and products in the future electronics field.

As BNM Institute of Technology, Bangalore enters its thirteenth year, I feel privileged to be part of every stage of its growth since its inception. In this article, I have tried to recall my presence as a part of BNMIT’s growing years.

SMART homes are soon going to be the reality with all the necessary technology available and changing lifestyle demanding it. Today, internet is being used for range of applications from banking needs to entertainment to day planners to appliance control. With internet capabilities and superior processing power of VLSI technology coupled with availability of wide range of sensors, it is no more a dream to have a SMART Home. This paper discussed the hardware and software technologies which can be used to realize the SMART Home. SMART Home hardware is defined as a Platform SoC identifying the specific differentiators which makes it a preferred candidate for such applications. Proposed PSoC is required to support many interfaces, standards to cater to wider functions of a Home to name a few Entertainments, healthcare, appliance control, environmental control, etc. User-friendly GUI, low power, and faster response will be the major differentiators of such platform SoCs. This paper attempts to identify the functional requirements of a basic Platform SOC and gives insight into PSoC architecture for SMART Home solution.

Images are signals produced by the imaging devices and can be digitized and processed by using the modern digital computers. Image processing is a subject that deals with the various mathematical and computing techniques/algorithms and the devices that can be used for improvement of image quality, processing of images and analysis. Image processing has a wide variety of applications in day-to-day activities and has gained popularity commercially and also in academic. In this paper, an introduction to the importance of images and imaging devices and their history and applications before the advent of digital computers and digital camera are provided in brief. The advantages of digital computers for digital image processing, uses and applications of image processing and the common image processing operations/techniques that are in use and practice are mentioned. Finally, the future scope and the research work that can be carried out in this area are highlighted for the prospective academicians, industrialists, and researchers, for the welfare of the society and mankind.

This paper discusses a generic flow on how an automated SV-based test bench environment which is randomized with constraints can verify a SOC effectively for its functionality and code coverage [

1

]. Today, in the era of multimillion gate ASICs, reusable intellectual property (IP), and system-on-a-chip (SoC) designs, verification [

1

] consumes about 70 % of the design effort. Automation lets you do something else while a machine completes a task autonomously, faster and with predictable results. Automation requires standard processes with well-defined inputs and outputs. Not all processes can be automated. Because of the variety of functions, interfaces, protocols, and transformations that must be verified, it is not possible to provide a general purpose automation solution for verification, given today’s technology. It is possible to automate some portion of the verification process, especially when applied to a narrow application domain. Tools automating various portions of the verification process are being introduced. Here, we have a SOC with a ARM multicore processor which talks to one of the peripherals, which is a flash memory (CODE FLASH and a DATA FLASH). The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence OVM libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the methodology [

2

] implemented in system verilog for SOC verification.

A 1.2 V 40 mA low-dropout regulator (LDO) for system-on-chip applications with 700 mV dropout is designed in Verilog-A. The proposed LDO provides fast line and load-transient responses with temperature-independent operation. The proposed LDO has been designed in Verilog-A using tsmc 65 nm CMOS technology and the total error of the output voltage due to line and load variations is low. The proposed LDO Design can be used to check the functional correctness of the SOC in the AMS verification flow [

1

].

A regulated cascode transimpendence preamplifier based low power, multichannel, fast front-end ASIC “ANUSPARSH” is designed for readout of ~3.6 million pick up strips of RPC detector of INO-ICAL experiment. This ASIC comprises eight front-end channels, each consisting of a regulated cascode preamplifier, two stages of differential amplifier providing total gain of ~7 mV/μA and a fast leading edge discriminator with LVDS output followed by a multiplexed fast analog buffer capable of driving 50 Ω cable. The regulated cascode preamplifier is used for the first time as readout of RPC detector exhibiting good impedance matching with the detector impedance of ~50 Ω over a wide frequency range. This ASIC is fabricated in 0.35 μm mixed CMOS process and tested successfully with the RPC detector. The front-end electronics requirements of INO-ICAL RPC detector and design approach for development of ANUSPARSH ASIC are presented along with test results when interfaced to the RPC detector.

Power minimization is the most required criteria in today’s world of electronics. Reversible logic provides an aid for low power. Fault-tolerant design is the one that enables a system to continue operation, possibly at a reduced level (degradation), rather than failing completely, when some part of the system fails. This helps in serving many safety critical applications. This paper provides a survey of an overview of latest advancements in research of reversible logic techniques at fault-tolerant level. It gives an overview of the methodologies used in the reversible engineering and the fault-tolerant gates used in them. An attempt is made to give a survey of the techniques used in different combinational logics and briefing them.

This paper presents a design of 4-channel Time-to-Digital Convertor (TDC) ASIC based on vernier ring oscillator technique. This technique implements two ring oscillators with very slight difference in time periods, which defines the resolution of TDC. The slight difference in time period is generated by using different fan-out load of the delay cell used to make respective ring oscillators. An on-chip calibration circuit provides the oscillator time period accurately for corrections, thereby reducing PVT (process, voltage, and temperature) variations. The TDC has been implemented using standard cell library of 0.35 μm commercial CMOS technology, achieving a resolution of 114 ps with a dynamic range of 1.8 μs and power consumption of 23 mW/channel.

Advancement in process technology has led to the emergence of MPSoC. At the same time, MPSoC leads to several design challenges. Thermal hot spots and temperature variations affect performance, reliability, power, and cooling cost. So, there is a need for a framework to act on elevation in temperature and temperature variations. In this paper, distributed thermal balancing migration scheme is applied for 3 × 3 tile-based NoC architecture. A balanced thermal profile is got by having workload balance on applying the migration policy only among the neighboring cores; thereby this scheme aims to have less communication overhead and less hot spot generation in the architecture.

Binary multiplier is one of the most time and power consuming architectures in an ALU. The performance efficiency of complex computations is determined by the multiplier algorithm used. Design of an efficient multiplier thus becomes important. An attempt has been made to implement an efficient multiplier using ancient computational techniques using charge recovery logic. This circuit is compared against the existing vedic multiplier circuits designed using conventional CMOS logic, to validate our claim. A 4 × 4 vedic multiplier using 2 N-2P type of charge recovery logic structure is implemented. The design and verification have been done using industry standard SPICE tools. The simulation results depict reduction in the average power consumption by 77.66 %.

The test cost and yield improvement are the major factors in the era of rapidly growing memory density and capacity. The Error-Correcting Codes (ECC) is widely used to detect and correct errors in memories. The Cyclic codes are one such code which belongs to the class of ECC with algebraic structure. This paper describes the algorithm and the memory architecture required to implement error detection and correction using cyclic code. It also presents a brief comparison between the single error correction technique based on cyclic code and another single error correction technique with code based on Reed–Muller matrix. These results are also compared with a multiple error correction technique based on modified matrix code. The results validate that cyclic codes have 80 % and 90 % lesser area, 90 and 50 % more correction efficiency when compared to the code based on Reed–Muller matrix and modified matrix codes, respectively, and around 45 % less delay when compared to the two codes.

Primarily, research in the design of high-performance standard cell libraries has been focused on drive strength selection of various logic gates. The paper proposes a novel technique of assessing load using on-chip path delay measurement and hence determines the drive strength of a standard cell in the paths iteratively. This approach is a three-phase approach viz. Synthesizing with standard default configuration of multidrive strengths, Drive strength assessment using load assessment by on-chip path delay measurement and reconfiguring the cells for proper drive strength by the synthesis process. The approach needs a multidrive standard cells library. This work focuses on determining the Drive strength of a standard cell by determining the load based on on-chip delay measurement though the other two steps explained in brief to give the complete perspective.

Time-to-digital converter is used to digitize the delay difference between two signals. In this paper, an implementation of 12-bit, 10 ps Vernier Ring Time-to-digital Converter (VRTDC) is presented. It uses Vernier delay cells and arbiters, placed in ring format and reuse them for the measurement of the input time interval. A prelogic unit is developed to decide leading and lagging signals, through which it is possible to measure both positive and negative phase difference. It is possible to achieve large detectable range, fine time measurement, small die size, and low-power consumption with the proposed VRTDC. The design is modeled using Verilog and synthesized using RTL Compiler targeting the design to 180 nm standard cell library.

Today’s System on Chips (SoC) are undoubtedly memory dominant, and it is predicted that the amount of space they occupy on the die will continue to increase, reaching up to 70 % by 2017 [

1

]. Built in self-test (BIST) has been the traditional technique for testing embedded memories over the years. Traditional BIST circuitry includes counter-based address generator which can be replaced by Adder-based address generator. The Adder-based address generator includes simple adder circuit to generate address and data for embedded MBIST. In this paper, adder-based address generator logic in BIST controller is proposed. This new idea for generating address and data has resulted in reduced area occupied by 40–68 % and the power dissipation by 83–86 % when compared with the traditional implementations.

Test power has emerged as an important design concern in nano-scaled technologies. The BIST circuitry for periodic self-test consumes significant power in hand-held electronic devices to increase battery lifetime. Reduced test power of a module allows parallel testing of multiple embedded cores in an IC. Peak and average power reduction during test contribute to enhanced reliability and improved yield. In this paper, we present circuit design methodologies to reduce test power in nano-scaled technologies. In addition to this advantage of reduced supply, testing concept is mentioned for initial testing which will give dual benefit of power and test time reduction.

A rectangular pulse-compression waveform having low-time side-lobes and zero mismatch loss is simulated. The waveform that is compressed with matched filter is continuous nonlinear frequency modulated (LFM), rectangular pulses. This is capable of achieving range side-lobe levels of better than−70 dB, suitable for use with satellite-borne precipitation radar.

Synchronous Code Division Multiple Access (CDMA) systems possess the advantages of efficient use of the spectral band width, resistance to co-channel interference and adaptability to variable traffic patterns. These advantages result from the usage of orthogonal spreading codes. The popularly used binary (2-level) spreading codes are Walsh, Gold, and Kasami codes. This paper proposes new multilevel (ML) orthogonal spreading codes constructed using ternary and quaternary Gray and Inverse Gray codes for multi-user Direct Sequence Code Division Multiple Access systems. The methodology explained in this paper allows to construct r-level 2n-length user codes. Multilevel spreading codes discussed in this paper are nonzero mean, varying power codes. An attempt is made to analyze these multilevel user codes through auto- and cross-correlation properties and bit error rate. Bit error rate performance of the proposed codes over Gaussian channel and their comparison with those of Walsh and Gold codes is presented in this paper. The proposed codes are found to be more suitable than the existing binary spreading codes.

The Low-Density Parity-Check (LDPC) code is a linear block code specified by a parity-check matrix H. The construction process of LDPC codes considers the parameters such as row and column-weights, rate, girth, and code length. Regularity of the codes provides the advantage like simplicity of hardware implementation and fast encoding. Large girth speeds the convergence of iterative decoding and improves performance. To increase girth of a code and avoid short cycles, the parity-check matrix H must be sufficiently sparse, and hence, the block length must be large. Hence, there is a need to develop method of constructing LDPC codes over a wide range of lengths, rates, and girths. In this paper, we introduce a novel method for constructing structured regular LDPC codes with different densities, rates, lengths, and girths using Gray-code representations. The advantage of this algorithm compared to other methods is its flexibility in terms of rates, lengths, and girths. LDPC codes with column-weight two have low computational complexity and are promising for data storage and partial response channels. Hence, a modified version of proposed algorithm, to construct a column-weight two LDPC codes with girth 8 and 12, is also presented in this paper.

In many multimedia applications, such as image storage and transmission image, compression plays a major role. The fundamental objective of image compression is to represent an image with least number of bits of an acceptable image quality. A technique based on second-generation curvelet transform and Back-Propagation Neural Network (BPNN) has been proposed. The image compression is accomplished by approximating curvelet coefficients using BPNN. By applying BPNN into compressing curvelet coefficients, we have proposed a new compression algorithm derived from characteristic of curvelet transform. Initially, the image is translated by fast discrete curvelet transform and then based on their statistical properties; different coding and quantization schemes are employed. Differential Pulse Code Modulation (DPCM) is employed to compress low-frequency band coefficients and BPNN is used to compress high-frequency band coefficients. Subsequently, vector quantization is performed on BPNN hidden layer coefficients, thereby resulting in a reconstructed image with less degradation at higher compression ratios. For a given bits per pixel (bpp), the Curvelet Transform with Back-Propagation Neural Network (BPNN) gives better performance in terms of Peak Signal-to-Noise Ratio (PSNR) and Computation Time (CT) when compared to Wavelet Transform with BPNN and JPEG.

This paper proposes a novel building block for designing Narrowband Bandpass Hairpin filter on PTFE laminate using the Radial stubs. The proposed circuit block mainly consists of coupled lines, microstrip lines, and the Radial stubs. The process starts with the theoretical design procedure of the filter. Tuning and optimization of the design is achieved using AWR Microwave office tool. Finally, the result of the optimized design is suitably presented for implementation. Insertion loss (IL) less than 5 dB and the Return loss (RL) better than 12 dB is achieved with the 11.65 GHz center frequency. Electro Magnetic (EM) simulation results show good agreement with the linear schematic model results.

This paper presents the design and simulation of 2-stage low-noise amplifier (LNA) for the application UHF range used for wireless communications and low-noise amplifier with bandwidth 800 M–1.2 GHz with optimization by using Enhancement Mode Pseudomorphic HEMT ATF34143 from Avago Technologies. The design and simulation uses lumped elements to implement the matching networks and proposed 2-stage is to achieve considerable gain. A 2-stage LNA has successfully designed and simulated with up to 33 dB forward gain, less than 0.58 dB noise figure and with good Voltage standing wave ratio (VSWR) from 1.5 to 1.6 at both input and output side by using advanced wireless revolution (AWR) Microwave office tool.

Basically, piezoelectric PZT, or lead zirconate titanate (Pb [Zr(x) Ti (1−x)] O3), is one of the world’s most widely used piezoelectric ceramic materials as Advanced Devices. When the deformation occurs in PZT than that can be used as an actuator to drive or control the devices. The present work deals with the development and control of a converter to drive piezoelectric actuators. To generate the required force in the piezoelectric ceramics, high voltages are needed. That can be achieved by designing a bidirectional buck-boost converter. The converter is controlled by means of PWM control strategy. The output of the converter is given to the power amplifier to get high-power output and gain. The design is made to drive the PZT Stack actuator. The design is verified by PSpice simulations.

Conducting polymers (PEDOT-PSS) belong to a category of materials which are peizoresitive and are used in variety of applications like strain gauges, gas sensors and many more. Since these conducting polymers are semiconductors, four probe measurement of film resistance is necessary to avoid errors due to contact resistance and spreading resistances. In a device, it is cumbersome to make four probe measurements and convenient to make two probe measurements. Large differences in the work function of polymers and contacts metals lead to rectifying contacts rather than ohmic contacts. A two probe measurement technique of making ohmic contacts to PEDOT-PSS film pristine and doped with 5 % DMSO is presented. It has been shown that by coating the contact probes with carbon nano powder, ohmic contacts can be achieved. This method can be employed for all conducting polymer measurements.

Upon exposure to gases, the surface properties of vapor-sensitive materials such as carbon nanotubes or conducting polymers change. These manifest as change in resistance or relative permittivity which are a measure of the gas concentration. A circular disk resonator using shift in resonant frequency as a measure to sense the gas has been reported for gas-sensing properties of carbon nanotubes. The sensor detected the presence of gases such as helium, oxygen, ammonia with a resonant frequency shift of 0.8, 2.3, and 3.55 MHz, respectively. Ring resonator is another promising resonating structure which can be explored for gas sensing applications. For gas sensing, based on resonant shift technique ring resonator offers more area for the gas to interact than the disk structure. Present research work aims at studying the resonating property of the ring resonator, analyze the performance, and compare with the existing results of the disk sensor using simulation tool HFSS. The gas adsorption is simulated using the change in relative permittivity (ε

r

) of the substrate. Simulation results indicate that ring resonator exhibits higher selectivity compared to disk resonator. This improved selectivity makes the ring resonator detect more variety of gases compared to disk.

The performance of submicron MOSFET with a thin conventional SiO

2

gate dielectric degrades due to increasing gate leakage currents. High-k dielectric materials are used as alternate gate dielectric to overcome the problem. The introduction of high-k dielectric induces high interface charges which degrades both the mobility and threshold voltage of MOS device. Simulation of devices with suitable tools and models helps us to mimic the device performance. Often errors are possible during selecting the models and regions of probing during simulation of results. This paper investigates the role of interface charges on carrier mobility and other MOSFET parameters. The probing positions for extraction of mobility are optimized by simulating the mobility at various positions along the channel and at various depths in the channel. From simulation results, it is shown that higher mobility is obtained by probing in the middle of the channel, 1 nm below the HfO

2

–Si interface. The performance of the high-k MOSFET with metal electrode and polysilicon electrode is also compared for various interface state charges.

Developing systems and devices that can recognize, interpret, and process human emotions are an interdisciplinary field involving computer science, psychology, and cognitive science. A system has been developed in order to formally categorize the emotions depending on facial expressions. The feature selection is done based on facial action coding system which is basically a contraction or relaxation of one or more face muscles. Our goal is to categorize the facial expression using image into six basic emotional states: Happy, Sad, Anger, Fear, Disgust, and Surprise. Extraction of facial features from eye, mouth, eyebrow, and nose is performed by employing an iterative search algorithm, on the edge information of the localized face region in binary scale. Finally, emotion class assignment is done by applying the extracted blocks as inputs to a feed-forward neural network trained by back-propagation algorithm.

The paper presents a DSP–FPGA-based parallel architecture for acquisition and compression of data in real time. The architecture is structured with high-performance DSP and acquisition hardware, implemented in FPGA. Hardware blocks for data acquisition with control logics, and FIFO are implemented in FPGA. FIFO interconnects DSP with acquisition hardware, running acquisition task in parallel for achieving maximum throughput. The data compression algorithms based on mean absolute deviation (μAD) is implemented on the DSP. The test results on field data show that the compression algorithm is very effectively implemented with the proposed architecture providing a very high compression ratio. The paper also presents the task management policy for implementing the scheme on DSP–FPGA hardware.

In this paper, an attempt is made to analyze the potential of contourlet transform (CT) for medical image watermarking. The effect of the embedding strength on the fidelity of the image is investigated. The algorithm is tested for its robustness against a few selected attacks like adding noise, cropping, and filtering attacks. Texture analysis is applied to understand the effect of watermarking in CT. Performance criteria such as root mean square error (RMSE), standard deviation (SDE), peak signal-to-noise ratio (PSNR), and normalized correlation (NC) are used to evaluate the potential of the proposed algorithm. The results show that the CT-based watermarking algorithm is comparable with the watermarking in the wavelet domain in terms of imperceptibility and robustness.

This paper presents the technique for denoising of partial discharge (PD) signals using genetic algorithm (GA) based on wavelet shrinkage. For the high voltage (HV) equipment in services, it is desired to perform PD tests when the equipment is in operation. The measurements, however, are seriously affected by the interference signals resulting from different sources. In order to enhance the sensitivity of a PD online monitoring system, many digital signal processing methods have been put forward for removal of noises. But to obtain the optimum denoising GA is applied. Here, first, optimum signal-to-noise ratio was obtained using modified wavelet technique (WT), and then, the same was obtained using GA and compared.

The image mosaicing can be used to combine two or more pictures extracted at different time from different sensors or different views. The general problem of mosaicing is to create a single seamless image by aligning a series of spatially overlapped images; the result is an image with a field of view greater than that of a single image. This paper proposes a framework for creating particularly convenient way to generate mosaics is by stitching together many ordinary photographs(capturing static scenes), proposed algorithm uses creating visually pleasing mosaics using a discrete cosine transform (DCT), it is a separable linear transformation and phase-correlation method to estimate the displacement between two adjacent images, DCT performs along a single dimension and the other dimension for an input images and also correlation-based scheme is used which operates in the discrete domain for finding the transformed coordinates (translational and rotational parameters) and use them for image mosaicing.

In this paper, we consider a novel cryptographic scheme, called visual cryptography, which can decode cascaded images without any cryptographic computations. We extend this scheme into an application, in which the two shares of a secret image are embedded with a text like names of the participants to whom these shares belong, using image fusion technique. This makes the shares more meaningful. The paper discusses the results obtained. The scheme is perfectly secure and easy to implement.

Diabetic retinopathy is an ocular disorder resulting in patients with long history of diabetes. It is a progressive disease characterized by numerous features like, microaneurysms (MA), hard exudates, soft exudates, veins bleeding, and hemorrhages. Presence of microaneurysms is the early signs of Diabetic retinopathy. In this paper, automatic detection of microaneurysms, that alternates the tedious and time-consuming manual process, is presented. Thresholding and morphological operations are used for microaneurysms detection from fundus images. In the first step, optic disk and blood vessels are eliminated to facilitate the detection of MA. Secondly, the candidate features are extracted based on their size. Experiments are performed on a set of 100 fundus images and have yielded encouraging results.

In the nuclear domain, strict adherence to standards and guides is mandatory for safety–critical software. IEC 60880 standard provides requirements for the safety–critical (Class IA) software of the computer-based I&C systems. But, each country has its own guides that need to be followed for licensing/certification of safety–critical software. This work aims to bring out the essential regulatory requirements for certification of software for Class IA systems in Indian nuclear domain. Also, this work attempts to determine whether there are any additional regulatory requirements for certification of safety–critical software vis-à-vis adhering to the IEC 60880. Finally, this work attempts to identify the objectives, fulfillment of which can form the basis for certification of Class IA software.

The CORDIC algorithm is an efficient method for computing trigonometric, logarithmic, hyperbolic, and exponential functions. It is used when hardware multipliers are not available, mainly in FPGAs. It finds innumerable applications in digital communication, image processing, artificial neural networks, and robotics. In this paper, the conventional CORDIC algorithm is optimized using selective rotation (SR) techniques which employ rotation selection algorithm (RSA) for faster convergence. A coarse LUT (Look up Table) is incorporated in the design to obtain coarse values which are fine-tuned using SR CORDIC stages. This architecture is simulated and verified as a part of a numerically controlled oscillator (NCO) using MATLAB and SIMULINK. This novel architecture is area-efficient and reduces the number of iterations required, to converge to a value, by 50 %.

A modeling of the image processing occurring at the level of the retina is sought to be developed. The aim is to show the advantages of using such a modeling in order to develop efficient and fast bio-inspired modules for low-level image processing in computer vision. The retinal model produces a contour-enhanced profile which is used to detect motion and orientation of contours. For this, a discrete Fourier transform–based approach has been developed.

Image retrieval has become an important aspect in today’s world as there is rapid growth of digital data. It is required to have efficient search system which delivers fast retrieval to cater to the need of end user with low computational cost and more accuracy. A new content-based search system is required to address the needs. In this paper, a new retrieval algorithm based on the statistical parameters like energy, standard deviation, and entropy of complex wavelets is presented. The performance is further enhanced by selective relevance feedback. The retrieval is carried out by decomposing the image using complex wavelet transform and computing the energy, standard deviation, moments, and the entropy of the subbands as feature vectors. The average retrieval accuracy of each of the class is improved by relevance feedback by training only the selected query images with poor retrieval accuracy.

The major difficulty in handling time series measurements is in identifying the system, whether it is purely deterministic, chaotic, or random. Proper identification of system characteristics and application of appropriate signal processing tools can lead to superior performance in signal analysis; especially when one handles real speech signals, these issues become even more important and crucial. Evidence for chaotic behavior with speech signals has been claimed and disputed. Over the past two decades, researchers have come out with efficient nonlinear dynamical tools applicable to time series. In this paper, different nonlinear dynamical tools like phase-space plot, running correlation dimension, and running Lyapunov exponent applied to speech signals are discussed which provide a convenient framework for speech signal analysis.

Biometric systems are becoming important, since they provide more efficient and reliable means to identity verification. In the recent studies, various biometric traits that include iris, face, gait, ear, palm, and knuckle joints have been investigated. Due to the intraclass variation, noisy sensor data, and susceptibility to spoofing attacks, the performance of these biometric systems is inaccurate. Gaze is one of the recent attractive topics in biometric research. In this paper, an attempt has been made to present an insight of different gaze estimation methods.

In a country like India, many of the documents such as office letters, checks, envelopes, forms, and other types of manuscripts are multiscript in nature. A document consisting of English script and a regional script is quite common. Hence, automatic recognition of scripts present in a multiscript document has a variety of practical and commercial applications in banks, post offices, reservation counters, libraries, etc. In this paper, a multiple feature-based approach is presented to identify the script type from a multiscript document. Features are extracted using Gabor filters, discrete cosine Transform, and wavelets of Daubechies family. Nine popular Indian scripts are considered for recognition in this paper. Experiments are performed to test the recognition accuracy of the proposed system at word level for bilingual scripts. Using neural network classifier, the average success rate is found to be 97 %.

Language identification is the task of automatically identifying the language of the speech signal uttered by an unknown speaker. An N language identification task is to classify an input speech utterance, spoken by unknown speaker and of unknown text, as belonging to one of the N languages. LID has applications as a front-end for machines of multi-lingual information retrieval system, multi-lingual speech recognition system and speech to speech translation system. In this paper, hidden Markov model is used for speech recognition and language modeling, i.e., bi-gram model which is the special case of N-gram model (n = 2 for bi-gram). The maximum-likelihood classifier is used to identify the language of given test speech.

Discrimination of handwritten and machine printed text in a scanned document image is an important process as the Optical Character Recognizers (OCRs) available are domain specific. In this paper, a novel approach has been proposed to discriminate handwritten and machine printed word components based on the structure. In the binarized form of the word component, due to the informative foreground overlay on the null background, transitions from 0-1 and 1-0 occur at the contour of the component structure. The count and occurrence of these transitions are used to discriminate handwritten and machine printed word components. The proposed method is robust and simple. Extensive experimentation has been conducted over a wide range of data samples (English words).

The objective of the electric utility is to deliver sinusoidal voltage at fairly constant magnitude throughout their system. As the load is more nonlinear, complexities also increase since these nonlinear loads produce harmonic currents. These harmonic currents result in voltage and current distortions that can adversely impact the system performance in different ways. With the increase in harmonic producing loads at the installation, severity to address the issue also increases. As an impact of these phenomena, two important concepts are to be borne in mind with regard to power system harmonics. They are harmonic current generated due to nonlinear loads such as computers and printers, and the second is the effect of harmonic currents [

1

,

2

]. In this work, the harmonics generated due to computer and printer is analyzed using power quality analyzer and harmonics are eliminated using wavelet transform.

This paper presents theoretical and practical application of a relatively unknown and rare image resampling technique called Lanczos resampling. Application of this method on satellite remote sensing images is considered. Image resampling is the mathematical technique used to create a new version of the image with a different width and/or height in pixels. Interpolation is the process of determining the values of a function at positions lying between its samples. Sampling the interpolated image is equivalent to interpolating the image with a sampled interpolating function. Image registration is the process of overlaying two or more images of the same scene taken at different times, from different viewpoints, and/or by different sensors. It geometrically aligns two images: the reference and sensed images. In the interaction between interpolation and sampling processes, aliases occur on some occasions. Majority of the registration methods consist of the steps like feature detection, feature matching, transform model estimation and image resampling and transformation. The proprietary softwares that are commercially available for image processing that are capable of doing image registration do not provide us with performance metrics for assessing the resampling methods used. Lanczos resampling method has not been used in the digital processing of remotely sensed satellite images by any of the open source and the proprietary software packages that are available until now. In this paper, we have applied performance metrics (on satellite images) for analyzing the performance of Lanczos resampling method. Comparison of Lanczos resampling method with other resampling methods, such as nearest neighborhood resampling, and sinc resampling, is done based on the metrics pertaining to entropy, mean relative error, and time. We propose that Lanczos resampling method to be a good method from qualitative and quantitative point of view when compared to the other two resampling methods. Also, it proves to be an optimal method for image resampling in the arena of remote sensing when compared to the other methods used. This, we hope, will enhance the understanding of the classified images’ characteristics in a quantitative manner.

Spatial filtering for mobile communications has attracted a lot of attention over the last decade and is currently considered a very promising technique that will help future cellular networks achieve their ambitious goals. One way to accomplish this is via array signal processing with algorithms which estimate the direction-of-arrival (DOA) of the received waves from the mobile users. This paper evaluates the performance of a number of DOA estimation algorithms. In all cases, a linear antenna array at the base station is assumed to be operating typical cellular environment.

Wireless sensor networks (WSNs) are one of the emerging network fields, with a tremendous prospect to research and contributing itself in a vast arena of applications. In any sort of network, the utmost priority is given to its security feature, since any means of communication demands the need of securing and safe guarding the sensitive data from the adversary. Even WSNs are also susceptible to any offenders attacks. In this paper, an attempt is made to design an perpetual proactive security scheme at the sink node using sniffing mechanism of intrusion detection system by studying the behavioral aspect of the sensor nodes due to attack and to monitor the system with an rescue mechanism.

Network processors in applications like cloud-based services call for sophisticated algorithms of traffic rate control mechanisms with different flexibility levels at different sites of the network. This paper presents the design, implementation, and analysis of distributed rate limiters, which work together to enforce a global rate limit across traffic aggregates at multiple sites, enabling the coordinated policing of a cloud-based service’s network traffic. The implementation enforces global limit and ensures that the congestion/responsiveness appears as though it has passed through a single shared rate limiter.

Network reliability analysis is usually based on minimal path or cut enumeration from which the associated reliability expressions are deduced. The cut-set method is a popular approach in the reliability analysis of many systems from simple configurations to complex configurations. The computational requirements necessary to determine the minimal cut-sets of a network depend mainly on the complexity of the system. A new algorithm is presented in this paper to determine the minimal cut-sets. This algorithm can handle both simple and complex networks and considers both unidirectional and bidirectional branches. The applicability of the proposed technique is illustrated by application to a more complicated system.

In the real-time network scenario, the network service providers need to ensure the quality of service (QoS) parameters. Network performance metrics (NPMs) are needed to measure the network performance and guarantee the QoS parameters like availability, delivery, latency, bandwidth which are also important for researchers and network equipment designers. One-way active measurement protocol (OWAMP) and two-way active measurement protocol (TWAMP) are the two active measurement approaches to measure the network performance. OWAMP measures one-way metrics and TWAMP measures two-way metrics. In this paper, currently prevalent active measurement methodologies and implementation of TWAMP approach are discussed. IPv6 TWAMP implementation for wireless networks is proposed, to obtain metrics, namely round-trip delay, two-way packet loss, jitter, packet reordering, packet duplication, and loss patterns.

The way of usage of computer is changed due to Internet and new technology called cloud computing. Cloud computing is the merging of another two new technologies like service-oriented architecture (SOA) and virtualization. The virtualization is gaining new goals and attracting those who need to perform the “miracle of multiplication,” as it is to fit more information into less space. The present survey paper is addressing about the virtualization which is one of the key features of the cloud computing, types of virtualization and its approaches, types of hypervisor, and building private cloud with the virtualization. The security of cloud computing is also discussed with new idea of introducing optical network as an access network and its devices in the data centers for an energy efficient centers.