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Published in:
2007 | OriginalPaper | Chapter
Process Variation-A ware Estimation of Static Leakage Power in Nano CMOS
Authors : B. P. Harish, Navakanta Bhat, Mahesh B. Patil
Published in: Simulation of Semiconductor Processes and Devices 2007
Publisher: Springer Vienna
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We present a statistical methodology for leakage power estimation, due to subthreshold and gate tunneling leakage, in the presence of process variations, for 65 nm CMOS. The circuit leakage power variations is analyzed by Monte Carlo (MC) simulations, by characterizing NAND gate library. A statistical “hybrid model” is proposed, to extend this methodology to a generic library. We demonstrate that hybrid model based statistical design results in up to 95% improvement in the prediction of worst to best corner leakage spread, with an error of less than 0.5%, with respect to worst case design.