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2012 | OriginalPaper | Chapter

3. Processor Cores

Authors : Kunio Uchiyama, Fumio Arakawa, Hironori Kasahara, Tohru Nojiri, Hideyuki Noda, Yasuhiro Tawara, Akio Idehara, Kenichi Iwata, Hiroaki Shikano

Published in: Heterogeneous Multicore Processor Technologies for Embedded Systems

Publisher: Springer New York

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Abstract

The processor cores described in this chapter are well tuned for embedded systems. They are SuperHTM RISC engine family processor cores (SH cores) as typical embedded CPU cores, flexible engine/generic ALU array (FE–GA or shortly called FE as flexible engine) as a reconfigurable processor core, MX core as a massively parallel SIMD-type processor, and video processing unit (VPU) as a video processing accelerator. We can implement heterogeneous multicore processor chips with them, and three implemented prototype chips, RP-1, RP-2, and RP-X, are introduced in the Chap. 4.

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previous chapter Heterogeneous Multicore Architecture
next chapter Chip Implementations
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Metadata
Title
Processor Cores
Authors
Kunio Uchiyama
Fumio Arakawa
Hironori Kasahara
Tohru Nojiri
Hideyuki Noda
Yasuhiro Tawara
Akio Idehara
Kenichi Iwata
Hiroaki Shikano
Copyright Year
2012
Publisher
Springer New York
Book
Heterogeneous Multicore Processor Technologies for Embedded Systems

Print ISBN: 978-1-4614-0283-1

Electronic ISBN: 978-1-4614-0284-8

Copyright Year: 2012

DOI
https://doi.org/10.1007/978-1-4614-0284-8_3