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2019 | OriginalPaper | Chapter

Programmable Architectures for Histogram of Oriented Gradients Processing

Authors : Colm Kelly, Roger Woods, Moslem Amiri, Fahad Siddiqui, Karen Rafferty

Published in: Handbook of Signal Processing Systems

Publisher: Springer International Publishing

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Abstract

There is an increasing demand for high performance image processing platforms based on field programmable gate array (FPGA). The Histogram of Orientated Gradients (HOG) algorithm is a feature descriptor algorithm used in object detection for many security applications. The chapter examines the implementation of this key algorithm using an FPGA-based soft-core architecture approach. Firstly, the HOG algorithm is described and its performance profiled from a computation and bandwidth perspective. Then the IPPro soft-core processor architecture is introduced and a number of mapping strategies are covered. A HOG implementation is demonstrated on a Zynq platform, resulting in a design operating at 15.36 fps; this compares favorably with the performance and resources of hand-crafted VHDL code.

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Metadata
Title
Programmable Architectures for Histogram of Oriented Gradients Processing
Authors
Colm Kelly
Roger Woods
Moslem Amiri
Fahad Siddiqui
Karen Rafferty
Copyright Year
2019
DOI
https://doi.org/10.1007/978-3-319-91734-4_18