Advertisement
Published in:
2015 | OriginalPaper | Chapter
Reconfigurable Packet FEC Architecture for Mobile Networks
Author : Wael M. El-Medany
Published in: Mobile Web and Intelligent Information Systems
Publisher: Springer International Publishing
Activate our intelligent search to find suitable subject content or patents.
Select sections of text to find matching patents with Artificial Intelligence. powered by
Select sections of text to find additional relevant content using AI-assisted search. powered by
This paper presents a reconfigurable hardware architecture of Forward Error Correction (FEC) coding algorithm for mobile networks, with high throughput on Field Programmable Gate Array (FPGA). The design can be reconfigured for different message length and different generator number, the encoder and decoder has been described using VHDL (VHSIC Hardware Description Language). The decoder has the ability to detect and correct different types and different numbers of errors based on the message length and the length of redundant data. The design has been simulated and tested using ModelSim PE student edition 10.4. Spartan 3 FPGA starter kit from Xilinx has been used for implementing and testing the design in a hardware level.