Reliability of CMOS Analog ICs

Table of Contents

1. Frontmatter

2. Chapter 1. Introduction

   Hakan Kuntman, Deniz Özenli, Fırat Kaçar, Yasin Özçelep

   Abstract

   The down-scaling of device dimensions in MOS technology will improve performance and packing density for VLSI circuits, but it will negatively affect the quality of the circuits because of reliability problems arising from several physical degradation effects. Although digital signal processing is becoming increasingly more powerful and many types of signal processing have indeed moved to digital domain due to the advances in IC technology, analog circuits are fundamentally necessary in many complex and high performance systems. This is caused by the reality that naturally occurring signals are analog. In other words, analog circuits act as a bridge between the real world and digital systems. In analog signal processing, many circuit topologies including active filters, oscillators, immittance simulators, etc. have been proposed in the literature.

   Today, modern CMOS technologies are continuously scaling down; but as a result of this, analog designers have serious reliability problems in their designs caused by physical effects such as hot-carrier injection, negative and positive bias temperature instability (N/PBTI), and time-dependent dielectric breakdown (TDDB). Therefore, it is an important factor estimating the deviations caused by these degradation mechanisms to obtain a robust design.

   In this respect, the structure of this book is as follows: The Introduction Section, Chap. 1, describing the basic concept is followed by Chap. 2 reflecting the definition of reliability analysis and statistical methods. The reliability model for PMOS and NMOS transistors based on statistical methods is given in this section. Demonstration on interesting application examples are given in Chap. 3 which reflects the behavior of a current source-loaded single stage amplifier, CMOS inverter, and CMOS OTA. The following part, Chap. 4, describes in detail the behavior of a CMOS OTA operating in subthreshold region which is also demonstrated with measurement results. Two different methods are given in this chapter. In addition, a CMOS degradation macromodel is also introduced in this section. Finally, Chap. 5 describes the reliability of power MOSFET circuits demonstrated by giving example circuits.

3. Chapter 2. The Reliability Model for PMOS and NMOS Transistors Based on Statistical Methods

   Hakan Kuntman, Deniz Özenli, Fırat Kaçar, Yasin Özçelep

   Abstract

   The use of statistical approach for reliable and optimal design of systems, including electronic systems, has become quite popular. Statistically designed experiments/simulations have been used extensively for estimating or demonstrating existing reliability by identifying the important parameters (factors) affecting reliability out of many potentially important ones. This statistical approach ensures the performance and safety of critical electronic systems employed for space, nuclear, automotive, defence, sub-marine and aerospace applications, to name a few. A statistical life model becomes more reliable, valuable, and useful, if it fits the experimental data quite well. In this section, we begin with the definition of the basic concept of reliability and lifetime estimation concepts. The reliability of a system is defined as the probability that it will perform its required function under stated conditions for a stated period of time.

4. Chapter 3. Demonstration of Proposed Method with Application Examples

   Hakan Kuntman, Deniz Özenli, Fırat Kaçar, Yasin Özçelep

   Abstract

   The reliability of a system is defined as the probability that it will perform its required function under stated conditions for a stated period of time. Rapid changes in the technology, shorter periods in product development, and higher reliabilities of products make accelerated life tests even more useful and important in the industry of today. Accelerated life tests are used to obtain timely information on the times to failure distributions of components and systems. Test units are subjected to higher than the usual levels of stress. Then the test results are extrapolated from the test conditions to the usual use conditions via physically reasonable statistical models. Models based on Weibull statistics are widely used as accelerated-life-test models in reliability engineering. In this context, the aim of this section is to propose a new representation of the hot-carrier degradation in threshold voltage of MOS transistors by applying the Weibull distribution to the experimental observations and to predict the device behavior after a long stress time. The advantages provided by the method proposed is demonstrated on different application examples, namely on the properties of a current source-loaded single stage amplifier, on a CMOS inverter and on a CMOS OTA, operating in subthreshold region.

5. Chapter 4. On the Degradation of OTA-C-Based CMOS Low-Power Filter Circuits for Biomedical Instrumentation

   Hakan Kuntman, Deniz Özenli, Fırat Kaçar, Yasin Özçelep

   Abstract

   The trend of microelectronic products in the biomedical field is toward higher functionality and miniaturization. As with other electronic devices, the miniaturization of biomedical devices is limited by the reliability of the manufactured product at a desired circuit density. Biomedical device failure or the disorder of biomedical device function during diagnosis and treatment processes may have extremely negative effects. Thus, in order to determine the ultimate performance, the reliability must be modeled for specific operating condition. In this section, hot-carrier-induced degradation of an electroencephalogram (EEG) band-pass filter structure composed of symmetrical CMOS OTAs is investigated. In this context, we propose a degraded transistor-based circuit degradation simulation method that is applicable to any CMOS device. The proposed method is based on the determination of the degraded transistors in the structure under stress conditions and includes the use of a degraded transistor model to adapt the experimental results of the transistor degradation to the simulation. In our study, we first simulated the symmetrical CMOS OTA degradation, considering the output current. Furthermore, to demonstrate the accuracy of the proposed method, the changes in the cutoff frequencies of the first- and second-order low-pass filters, composed of symmetrical CMOS OTAs, were investigated.

6. Chapter 5. Power MOSFET Degradation and Statistical Investigation of the Degradation Effect on DC–DC Converters and Converter Parameters

   Hakan Kuntman, Deniz Özenli, Fırat Kaçar, Yasin Özçelep

   Abstract

   Electrical over stress-induced power MOSFET degradation and its effects on DC–DC converters were examined in this chapter. Power MOSFETs experimentally operated above normal operating conditions and stress-induced changes in transistor parameters extracted. Switch-mode DC–DC converters are simulated to show degraded power MOSFET effects statistically and effects on converter parameters. This section describes a simple and prognostic electrical stress-induced mobility degradation model for MOS transistors. For this purpose, we performed electrical stress experiments on CoolMOS transistors which is a type of power MOSFETs. We determined the stress-induced changes in transistor parameters. We introduced a quantity C_r (mobility decreasing coefficient) which provides accurate model and predict the mobility degradation in time independently from effects of process or operational changes such as oxide thickness, substrate doping, and applied voltages on transistor.

7. Backmatter