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2020 | OriginalPaper | Chapter

RiCaSi: Rigorous Cache Side Channel Mitigation via Selective Circuit Compilation

Authors : Heiko Mantel, Lukas Scheidel, Thomas Schneider, Alexandra Weber, Christian Weinert, Tim Weißmantel

Published in: Cryptology and Network Security

Publisher: Springer International Publishing

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Abstract

Cache side channels constitute a persistent threat to crypto implementations. In particular, block ciphers are prone to attacks when implemented with a simple lookup-table approach. Implementing crypto as software evaluations of circuits avoids this threat but is very costly.
We propose an approach that combines program analysis and circuit compilation to support the selective hardening of regular C implementations against cache side channels. We implement this approach in our toolchain RiCaSi. RiCaSi avoids unnecessary complexity and overhead if it can derive sufficiently strong security guarantees for the original implementation. If necessary, RiCaSi produces a circuit-based, hardened implementation. For this, it leverages established circuit-compilation technology from the area of secure computation. A final program analysis step ensures that the hardening is, indeed, effective.

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previous chapter Integral Cryptanalysis of Reduced-Round Tweakable TWINE
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Metadata
Title
RiCaSi: Rigorous Cache Side Channel Mitigation via Selective Circuit Compilation
Authors
Heiko Mantel
Lukas Scheidel
Thomas Schneider
Alexandra Weber
Christian Weinert
Tim Weißmantel
Copyright Year
2020
Book
Cryptology and Network Security

Print ISBN: 978-3-030-65410-8

Electronic ISBN: 978-3-030-65411-5

Copyright Year: 2020

DOI
https://doi.org/10.1007/978-3-030-65411-5_25

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