Skip to main content
Disciplines
Automotive Business IT + Informatics Construction + Real Estate Electrical Engineering + Electronics Energy + Sustainability Insurance + Risk Finance + Banking Management + Leadership Marketing + Sales Mechanical Engineering + Materials
Events
DE
EN
Books
Journals
Topic Page
Marketing
Start single access now
Access for companies
EXTENDED SEARCH
Log in
Top
Journal of Electronic Testing
Published in: Journal of Electronic Testing 1/2013

01-02-2013

SEU Fault-Injection in VHDL-Based Processors: A Case Study

Authors: Wassim Mansour, Raoul Velazco

Published in: Journal of Electronic Testing | Issue 1/2013

Log in

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

Evaluating the sensibility of a given circuit with respect to soft errors became a main issue especially if it is intended to operate in space or at high altitudes. A hardware/software (HW/SW) approach to study the effects of soft errors by fault injection in the VHDL model of a CPU (Control Processor Unit) is presented and illustrated by results obtained for a LEON3 processor. The LEON3 is set to execute two benchmark algorithms. The first one is a typical 3x3 matrix multiplication, whereas the second one is a self-converging algorithm which is intended to provide correct results even if a failure occurs in the middle of the execution. The results of fault-injection campaigns targeting the register file unit of the processor are compared to those issued from a state-of-the-art method, the C.E.U. (Code Emulated Upset). One of the main advantages of the proposed method is the larger targeted Single Event Upset (SEU) sensitive area leading to improved error rate predictions.
previous article Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints
next article A New Analog Circuit Fault Diagnosis Method Based on Improved Mahalanobis Distance

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

inform now
Show more products
Literature
1.
Aguirre MA et al (2005) FT-UNSHADES: A new system for SEU injection, analysis and diagnostics over post synthesis netlist, in Proc. NASA Military and Aerospace Programmable Logic Devices, MAPLD, Washington, D.C., September 2005
2.
Alderighi M et al (2010) Experimental validation of fault injection analysis by the FLIPPER tool. Trans Nucl Sci 57(4):2129–2134CrossRef
3.
Arlat J et al (1990) Fault-injection for dependability validation—a methodology and some applications. Trans IEEE Softw Eng 16:166–182
4.
Baumann R (2005) Soft errors in advanced computer systems. IEEE Des Test Comput 22(3):258–266CrossRef
5.
Civera P et al (2001) Exploiting FPGA-based techniques for fault-injection campaigns on VLSI circuits. IEEE International Symposium on Defect and Fault Tolerance in VLSI systems pp. 250–258
6.
Entrena L et al (2012) Soft error sensitivity evaluation of microprocessors by multilevel emulation-based fault injection. Trans. Comput, pp.313–322
7.
Faure F, Peronnard P, Velazco R (2002) Thesic+: a flexible system for SEE testing, in Proc. of RADECS
8.
Folkesson et al (1998) A comparison of simulation based and scan chain implemented fault injection. Proc. Of the Annual International Symposium on Fault-Tolerant Computing, pp. 284–293
9.
Guzman-Miranda H et al (2008) FT-UNSHADES-up: A platform for the analysis and optimal hardening of embedded systems in radiation environments. IEEE International Symposium on Industrial Electronics, pp.2276-2281
10.
Jeitler M et al (2009) FuSE—a hardware accelerated HDL fault injection tool. In SPL. 5th Southern Conference on Programmable Logic. pp. 84–94, April 2009.
11.
Johnston AH (2000) Scaling and technology issues for soft error rates. Proceedings of 4th Annual Research Conference on Reliability, Stanford University, October 2000
12.
LopezOngil C et al (2007) A unified environment for fault injection at any design level based emulation. IEEE Trans Nucl Sci 54:946–950CrossRef
13.
Ma T, Dressendorfer P (1989) Ionizing radiation effects in MOS devices and circuits. Wiley, New York
14.
Madeira H et al (1994) RIFLE: a general purpose pin-level fault injector. Proc of the European Dependable Computing Conference. pp. 199–216.
15.
Mavis DG, Eaton P (2002) Soft error rate mitigation technqiues for modern microcircuits, in Proc. of International Reliability Symp., (IRPS), pp. 216–225
16.
Mohammadi A et al (2012) SCFIT: A FPGA-based fault injection technique for SEU fault model, in Proc. of the Design, Autimation and Test in europe Conference and Exhibition (DATE), pp.586-589
17.
Naviner L et al (2011) FIFA: A fault-injection-fault-analysis-based tool for reliability assessment at RTL level. Microelectron Reliab 51:1459–1463CrossRef
18.
Nicolaidis M (2010) Soft errors in modern electronic systems. SPRINGER Ed., ISBN 978-1-4419-6992-7
19.
Normand E (1966) Single-event effects in avionics. IEEE Trans Nucl Sci 43(2):461–474CrossRef
20.
Peronnard P (2009) Etude de cas: caractérisation d’un processeur complexe de type PowerPC, chapter in Méthodes et outils pour l’évaluation de la sensibilité de circuits intégrés avancés face aux radiations naturelles, October 2009
21.
Rahbaran B et al (2004) Built-in fault injection in hardware- the FIDYCO example. Proc. of the Second IEEE International Workshop on Electronic Design, Test and Application, pp. 327–332, January 2004
22.
Rezgui S, Velazco R, Ecoffet R, Rodriguez S, Mingo JR (2001) Estimating error rates in processor-based architectures. IEEE Trans Nucl Sci 48:1680–1687CrossRef
23.
Rousselle C et al (2001) A register-transfer-level fault simulator for permanent faults in embedded processors, in Proc. of DATE2001 Conference, Munich, Germany
24.
Shokralla-Shirazi M et al (2008) FPGA-based fault injection into synthesizable verilog HDL models. The Second International Conference on Secure System Integration Reliability Improvement, SSIRI
25.
Sieh V et al (1997) VERIFY: evaluation of reliability using VHDL-models with embedded fault description. Proc. Of the International Symposium on Fault-Tolerant Computing, pp. 32–36, June 1997
26.
Velazco R, Rezgui S, Ecoffet R (2000) Predicting error rate for microprocessor-based digital architectures through c.e.u. (code emulating upsets) injection. IEEE Trans Nucl Sci 47:2405–2411CrossRef
27.
Velazco R et al (2010) Integrated circuit qualification for space and ground-level applications: accelerated tests and error-rate predictions. Chapter, series: frontiers in electronics testing, vol. 41
28.
Velazco R et al (2011) Robustness with respect to SEUs of a self-converging algorithm, in Proc. of LATW 2011 (Latin American Test Workshop), Porto Galinhas, Brazil, 28–30 March 2011
29.
Velazco R et al (2011) Improving SEU fault tolerance capabilities of a self-converging algorithm, in Proc. of RADECS 2011 (RADiation Effects on Circuits and Systems), Sevilla, spainl, 19–23 September 2011
30.
Zhang H et al (2008) FITVS: A FPGA-based emulation tool for high efficiency hardness evaluation, in International Symposium on Parallel and Distributed Processing with Applications, pp.525-531
Metadata
Title
SEU Fault-Injection in VHDL-Based Processors: A Case Study
Authors
Wassim Mansour
Raoul Velazco
Publication date
01-02-2013
Publisher
Springer US
Published in
Journal of Electronic Testing / Issue 1/2013
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-013-5351-6

Other articles of this Issue 1/2013

Journal of Electronic Testing 1/2013 Go to the issue

OriginalPaper

Testing of Synchronizers in Asynchronous FIFO

Announcement

New Editors, 2013

OriginalPaper

A New Analog Circuit Fault Diagnosis Method Based on Improved Mahalanobis Distance

OriginalPaper

Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints

OriginalPaper

Eliminating the Timing Penalty of Scan

News

Test Technology Newsletter