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Published in:
2007 | OriginalPaper | Chapter
Simulation Study of Multiple FIN FinFET Design for 32nm Technology Node and Beyond
Authors : Xinlin Wang, Andres Bryant, Omer Dokumaci, Phil Oldiges, Wilfried Haensch
Published in: Simulation of Semiconductor Processes and Devices 2007
Publisher: Springer Vienna
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In this work, we investigate multiple FIN FinFET source/drain designs to reduce series resistance and source/drain-to-gate capacitance. The tradeoffs between the increased parasitic capacitance and reduced parasitic resistance are explored using 3D device simulations.