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Published in:
2008 | OriginalPaper | Chapter
Simulation vs. Formal: Absorb What Is Useful; Reject What Is Useless
Author : Alan J. Hu
Published in: Hardware and Software: Verification and Testing
Publisher: Springer Berlin Heidelberg
This short paper is the result of the invited talk I gave at the 2007 Haifa Verification Conference. Its purpose is to briefly summarize the main points of my talk and to provide background references. The original talk abstract was, “Dynamic verification (simulation, emulation) and formal verification often live in separate worlds, with minimal interaction between the two camps, yet both have unique strengths that could complement the other. In this talk, I’ll briefly enumerate what I believe are the best aspects of each verification style, and then explore some possibilities for drawing on the strengths of both camps.”
