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Published in:
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2018 | OriginalPaper | Chapter

6. SONOS 1Tr eFlash Memory

Authors : Hidenori Mitani, Ken Matsubara

Published in: Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations

Publisher: Springer International Publishing

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Abstract

In this chapter, a brief history of SONOS flash technology is introduced followed by the details of one-transistor SONOS (1Tr-SONOS) technology. Memory-cell structure, basic cell-operation principles and fabrication process are described. Then basic array architecture and read/program/erase operations are explained with corresponding peripheral circuits. A disturb mode in program and erase operations is also discussed. Finally, advanced circuit techniques to expand application range, especially for automotive use with high reliability and low energy consumption are described.

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previous chapter Split-Gate Floating Poly SuperFlash® Memory Technology, Design, and Reliability
next chapter SONOS Split-Gate eFlash Memory
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Metadata
Title
SONOS 1Tr eFlash Memory
Authors
Hidenori Mitani
Ken Matsubara
Copyright Year
2018
Book
Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations

Print ISBN: 978-3-319-55305-4

Electronic ISBN: 978-3-319-55306-1

Copyright Year: 2018

DOI
https://doi.org/10.1007/978-3-319-55306-1_6