Speeding-Up Radio-Frequency Integrated Circuit Sizing with Neural Networks

Despite the efforts in the past few decades years, the lack of automation in analog, and more specifically, radio-frequency (RF) integrated circuit (IC) design creates a large design productivity gap. The level of automation provided by electronic design automation (EDA) tools for analog IC design is not even close to the level of automation found in digital design. Moreover, as analog IC design follows very heterogeneously and knowledge-intensive approaches, its automation is still an open research field. In this chapter, we introduce the analog/RF IC design problem and explore how the advances in machine learning (ML) can pave the way to assist existent EDA tools.

This chapter presents and analyzes the state-of-the-art methodologies for analog and radio-frequency (RF) integrated circuit (IC) sizing automation. It starts by overviewing the main tools used to automate analog/RF circuit sizing in the past few decades, which can be divided into two major categories, i.e., knowledge-based and optimization-based. Afterward, related work using machine learning (ML) and deep learning (DL) techniques to enhance simulation-based optimizations will be presented and discussed, along with other works that tackle pure ML/DL-based sizing. Finally, a case study is introduced and some short conclusions taken, in order to set the starting point of the developments proposed in this book.

Internet-of-things applications push radio-frequency (RF) integrated circuit (IC) design in deep nanometer technologies. Particularly, voltage-controlled oscillators (VCOs), which play a crucial role in ultralow-power radios, different tradeoffs between power, phase noise, range, frequency pushing, and silicon area, turn their design into a cumbersome task without the assistance of electronic design automation (EDA), a field where simulation-based sizing tools are acknowledged as the way to go (Afacan and Dündar in Integr VLSI 67:162–169, 2019 [1]; Passos in Integr VLSI 63:351–361, 2018 [2]; Liao and Zhang in ASPDAC, 2017 [3]). However, as the simulation times increase exponentially with the process, voltage, and temperature (PVT) corners or extracted netlists from layout (Passos et al. in IEEE Access 8:51601–51609, 2020 [4]; Martins et al. in TCAS-I 67:3965–3977, 2020 [5]), complex RF circuit topologies pose unprecedented challenges to the application of these tools. Some of the problems lie in when to set a timeout on the VCO convergence attempts (whose simulator may attempt to converge forever), or, as the guessed oscillation frequencies have a strong correlation with the steady-state analysis output, good designs may still be lost without simulating multiple guesses (Martins in TCAS-I 67:3965–3977, 2020 [5]). As overviewed in Chap. 2, recent development in artificial neural networks (ANNs) are offering new alternatives to the design automation of analog and RF ICs (Afacan et al. in Integr VLSI 77:113–130, 2021 [6]), such as in modeling (Suissa et al. in IEEE TCAD 29:839–844, 2010 [7]), mapping from devices’ sizes to circuits’ performances (Wolfe and Vemuri in IEEE TCAD 22:198–212, 2003 [8]; Alpaydin et al. in IEEE Trans Evol Comput 7:240–252, 2003 [9]; Liu et al. in Proceedings 2002 design automation conference, pp 437–442, 2002 [10]), mapping from specifications to the sizing (Lourenço et al. in 16th International conference on synthesis, modeling, analysis and simulation methods and applications to circuit design, pp 13–16, July 2019 [11]), layout generation (Zhu et al. in Proceedings of the ICCAD, 2019 [12]; Guerra et al. in International conference on SMACD, Lausanne, Switzerland, July 2019 [13]; Gusmão et al. in IEEE International symposium on circuits and systems, Seville, Spain, Oct 2020 [14]; Gusmão et al. in Expert systems with applications. Elsevier, Amsterdam, 2022 [15]; Gusmão et al. in Applied soft computing, vol 115. Elsevier, Amsterdam, 108188, 2022 [16]; Gusmão et al. in ACM/IEEE design automation conference (DAC), San Francisco, USA, Dec 2021 [17]) or even fault testing (Andraud et al. in IEEE TCAS-I Reg Pap 63:2022–2035, 2016 [18]). This chapter proposes two deep learning (DL) models to assist the PVT-inclusive simulation-based sizing process of RF ICs, specifically, VCOs. Given specific devices’ dimensions, the 1st model classifies the likeability of the circuit to convergence for nominal and PVT corners, bypassing solutions that will hardly produce valuable information for the optimization process. The 2nd model predicts the VCOs’ oscillating frequency, providing a better guess for the simulator. The methodology is tested on state-of-the-art VCOs, reducing up to 19% of the workload of the circuit simulator, ultimately saving almost 5 days of computational effort and improving the optimization result.

As overview in Chap. 2 of this book, recent advances in machine learning (ML) and deep learning (DL), and more specifically, artificial neural networks (ANNs), are offering new alternatives to the design automation of analog and radio-frequency (RF) integrated circuits (ICs) (Afacan et al. in Integr VLSI 77:113–130, 2021 [1]). DL is already being used on several fronts, e.g., modeling (Suissa in IEEE TCAD 29:839–844, 2010 [2]), mapping from devices’ sizes to circuits’ performances (Wolfe and Vemuri in IEEE TCAD 22:198–212, 2003 [3]; Alpaydin et al. in IEEE Trans Evol Comput 7:240–252, 2003 [4]; Liu et al. in Proceedings 2002 design automation conference, pp 437–442, 2002 [5]), mapping from specifications to the sizing (Lourenço et al. in 16th International conference on synthesis, modeling, analysis and simulation methods and applications to circuit design, pp 13–16, 2019 [6]), layout generation (Zhu et al. in Proceedings of the ICCAD, 2019 [7]; Guerra et al. in International conference on SMACD, Lausanne, Switzerland, July 2019 [8]; Gusmão et al. in IEEE International symposium on circuits and systems, Seville, Spain, Oct 2020 [9]; Gusmão et al. in Expert systems with applications. Elsevier, Amsterdam, 2022 [10]; Gusmão et al. in Applied soft computing. Elsevier, Amsterdam, 2022 [11]; Gusmão et al. in ACM/IEEE design automation conference (DAC), San Francisco, USA, Dec 2021 [12]) or even fault testing (Andraud et al. in IEEE TCAS-I Reg Pap 63:2022–2035, 2016 [13]). The work proposed in this chapter follows the most recent trials on ML-assisted simulation-based sizing by proposing a regressor that estimates the complete set of process, voltage, and temperature (PVT) performances of complex RF IC topologies. The proposed PVT regressor takes at the input the circuit’s sizing and the accurate performance figures in nominal conditions. When embedded into a simulation-based sizing loop, it drastically reduces the total optimization time required. Tests on the class C/D voltage-controlled oscillator show a 79% improvement in workload.