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Published in: The Journal of Supercomputing 7/2021

02-01-2021

ST-CAC: a low-cost crosstalk avoidance coding mechanism based on three-valued numerical system

Authors: Zahra Shirmohammadi, Ata Khorami, Martin Eugenio Omana

Published in: The Journal of Supercomputing | Issue 7/2021

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Abstract

Appearances of specific transition patterns during data transfer in bus lines of modern high-performance computing systems, such as communicating structures of accelerators for deep convolutional neural networks, commercial Network on Chips, and memories, can lead to crosstalk faults. With the shrinkage of technology size, crosstalk faults occurrence boosts and leads to degradation of reliability and performance, as well as the increasing power consumption of lines. One effective way to alleviate crosstalk faults is to avoid the appearance of these specific transition patterns by using numerical-based crosstalk avoidance codes (CACs). However, a serious problem with numerical-based CACs is their overheads in terms of required additional bus lines for representing code words. To solve this problem, in this paper we present a novel CAC that is based on the use of three symbols (three-value) to represent the code words in the bus lines, rather than classical binary CACs based on binary, i.e., 0 and 1 symbols. Our proposed CAC, named summation-based tri-value crosstalk avoidance code (ST-CAC), reduces the worst-case delay in bus lines with respect to binary CACs, and it can efficiently be applied to any arbitrary channel width of lines. The use of three symbols to represent code words in ST-CAC enables to increase the number of code words of a numerical system without increasing the number of required bus lines significantly. The experimental results show that CACs based on the use of three symbols can reduce the number of additional lines compared to binary CACs by 33%. Moreover, we show in the paper, that the delay of wires in the presence our ST-CAC can reduce by 33% with respect to state-of-the-art binary value CACs.

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Literature
1.
go back to reference Choi W, Duraisamy K, Kim RG, Doppa JR, Pande PP, Marculescu D, Marculescu R (2018) On-chip communication network for efficient training of deep convolutional networks on heterogeneous manycore systems. IEEE Trans Comput 67(5):672–686MathSciNetCrossRef Choi W, Duraisamy K, Kim RG, Doppa JR, Pande PP, Marculescu D, Marculescu R (2018) On-chip communication network for efficient training of deep convolutional networks on heterogeneous manycore systems. IEEE Trans Comput 67(5):672–686MathSciNetCrossRef
2.
go back to reference Pd SM, Lin J, Zhu S, Yin Y, Liu X, Huang X, Song C, Zhang W, Yan M, Yu Z et al (2017) A scalable network-on-chip microprocessor with 2.5 d integrated memory and accelerator. IEEE Trans Circuits Syst I Regul Pap 64(6):1432–1443CrossRef Pd SM, Lin J, Zhu S, Yin Y, Liu X, Huang X, Song C, Zhang W, Yan M, Yu Z et al (2017) A scalable network-on-chip microprocessor with 2.5 d integrated memory and accelerator. IEEE Trans Circuits Syst I Regul Pap 64(6):1432–1443CrossRef
4.
go back to reference Benini L, De Micheli G (2002) Networks on chips: a new soc paradigm. IEEE Trans Comput 35(1):70–78 Benini L, De Micheli G (2002) Networks on chips: a new soc paradigm. IEEE Trans Comput 35(1):70–78
5.
go back to reference Sridhara SR, Shanbhag NR (2007) Coding for reliable on-chip buses: a class of fundamental bounds and practical codes. IEEE Trans CAD Integr Circuits Syst 26(5):977–982CrossRef Sridhara SR, Shanbhag NR (2007) Coding for reliable on-chip buses: a class of fundamental bounds and practical codes. IEEE Trans CAD Integr Circuits Syst 26(5):977–982CrossRef
6.
go back to reference Tehranipour MH, Ahmed N, Nourani M (2003) Testing soc interconnects for signal integrity using boundary scan. In: Proceedings of 21st VLSI Test Symposium. IEEE, pp 158–163 Tehranipour MH, Ahmed N, Nourani M (2003) Testing soc interconnects for signal integrity using boundary scan. In: Proceedings of 21st VLSI Test Symposium. IEEE, pp 158–163
7.
go back to reference Zimmer H, Jantsch A (2003) A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip. In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. ACM, 2003, pp 188–193 Zimmer H, Jantsch A (2003) A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip. In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. ACM, 2003, pp 188–193
8.
go back to reference Frantz AP, Kastensmidt FL, Carro L, Cota E (2006) Dependable network-on-chip router able to simultaneously tolerate soft errors and crosstalk. In: IEEE International Test Conference, 2006. ITC’06. IEEE, pp 1–9 Frantz AP, Kastensmidt FL, Carro L, Cota E (2006) Dependable network-on-chip router able to simultaneously tolerate soft errors and crosstalk. In: IEEE International Test Conference, 2006. ITC’06. IEEE, pp 1–9
9.
go back to reference Agarwal K, Sylvester D, Blaauw D (2006) Modeling and analysis of crosstalk noise in coupled rlc interconnects. IEEE Trans Comput Aided Des Integr Circuits Syst 25(5):892–901CrossRef Agarwal K, Sylvester D, Blaauw D (2006) Modeling and analysis of crosstalk noise in coupled rlc interconnects. IEEE Trans Comput Aided Des Integr Circuits Syst 25(5):892–901CrossRef
10.
go back to reference Zhang J, Friedman EG (2004) Effect of shield insertion on reducing crosstalk noise between coupled interconnects. In: Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS’04. IEEE, vol 2, pp II–529 Zhang J, Friedman EG (2004) Effect of shield insertion on reducing crosstalk noise between coupled interconnects. In: Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS’04. IEEE, vol 2, pp II–529
11.
go back to reference Kaul H, Seo J-s, Anders M, Sylvester D, Krishnamurthy R (2008) A robust alternate repeater technique for high performance busses in the multi-core era. In: IEEE International Symposium on Circuits and Systems, 2008. ISCAS. IEEE, pp 372–375 Kaul H, Seo J-s, Anders M, Sylvester D, Krishnamurthy R (2008) A robust alternate repeater technique for high performance busses in the multi-core era. In: IEEE International Symposium on Circuits and Systems, 2008. ISCAS. IEEE, pp 372–375
12.
go back to reference Ghoneima M, Ismail YI, Khellah MM, Tschanz JW, De V (2006) Reducing the effective coupling capacitance in buses using threshold voltage adjustment techniques. IEEE Trans Circuits Syst I Regul Pap 53(9):1928–1933CrossRef Ghoneima M, Ismail YI, Khellah MM, Tschanz JW, De V (2006) Reducing the effective coupling capacitance in buses using threshold voltage adjustment techniques. IEEE Trans Circuits Syst I Regul Pap 53(9):1928–1933CrossRef
13.
go back to reference Wu X, Yan Z (2011) Efficient codec designs for crosstalk avoidance codes based on numeral systems. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(4):548–558MathSciNetCrossRef Wu X, Yan Z (2011) Efficient codec designs for crosstalk avoidance codes based on numeral systems. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(4):548–558MathSciNetCrossRef
14.
go back to reference Murali S, Theocharides T, Vijaykrishnan N, Irwin MJ, Benini L, De Micheli G (2005) Analysis of error recovery schemes for networks on chips. IEEE Des Test Comput 22(5):434–442CrossRef Murali S, Theocharides T, Vijaykrishnan N, Irwin MJ, Benini L, De Micheli G (2005) Analysis of error recovery schemes for networks on chips. IEEE Des Test Comput 22(5):434–442CrossRef
15.
go back to reference Duan C, Calle VHC, Khatri SP (2009) Efficient on-chip crosstalk avoidance codec design. IEEE Trans Very Large Scale Integr VLSI Syst 17(4):551–560CrossRef Duan C, Calle VHC, Khatri SP (2009) Efficient on-chip crosstalk avoidance codec design. IEEE Trans Very Large Scale Integr VLSI Syst 17(4):551–560CrossRef
16.
go back to reference Duan C, Tirumala A, Khatri SP (2001) Analysis and avoidance of cross-talk in on-chip buses. In: Hot Interconnects 9, 2001. IEEE, pp 133–138 Duan C, Tirumala A, Khatri SP (2001) Analysis and avoidance of cross-talk in on-chip buses. In: Hot Interconnects 9, 2001. IEEE, pp 133–138
17.
go back to reference Duan C, LaMeres BJ, Khatri SP (2010) On and off-chip crosstalk avoidance in VLSI design. Springer, BerlinCrossRef Duan C, LaMeres BJ, Khatri SP (2010) On and off-chip crosstalk avoidance in VLSI design. Springer, BerlinCrossRef
18.
go back to reference Sotiriadis PP, Chandrakasan A (2001) Reducing bus delay in submicron technology using coding. In: Proceedings of the 2001 Asia and South Pacific Design Automation Conference. ACM, 2001, pp 109–114 Sotiriadis PP, Chandrakasan A (2001) Reducing bus delay in submicron technology using coding. In: Proceedings of the 2001 Asia and South Pacific Design Automation Conference. ACM, 2001, pp 109–114
19.
go back to reference Shirmohammadi Z, Miremadi SG (2015) S2ap: An efficient numerical-based crosstalk avoidance code for reliable data transfer of NOCS. In: 10th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). IEEE, pp 1–6 Shirmohammadi Z, Miremadi SG (2015) S2ap: An efficient numerical-based crosstalk avoidance code for reliable data transfer of NOCS. In: 10th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). IEEE, pp 1–6
20.
go back to reference Shirmohammadi Z, Miremadi SG (2016) On designing an efficient numerical-based forbidden pattern free crosstalk avoidance codec for reliable data transfer of nocs. Microelectron Reliab 63:304–313CrossRef Shirmohammadi Z, Miremadi SG (2016) On designing an efficient numerical-based forbidden pattern free crosstalk avoidance codec for reliable data transfer of nocs. Microelectron Reliab 63:304–313CrossRef
21.
go back to reference Chang C-S, Cheng J, Huang T-K, Huang X-C, Lee D-S, Chen C-Y (2015) Bit-stuffing algorithms for crosstalk avoidance in high-speed switching. IEEE Trans Comput 64(12):3404–3416MathSciNetCrossRef Chang C-S, Cheng J, Huang T-K, Huang X-C, Lee D-S, Chen C-Y (2015) Bit-stuffing algorithms for crosstalk avoidance in high-speed switching. IEEE Trans Comput 64(12):3404–3416MathSciNetCrossRef
22.
go back to reference Shirmohammadi Z, Mozafari F, Miremadi S-G (2017) An efficient numerical-based crosstalk avoidance codec design for nocs. Microprocess Microsyst 50:127–137CrossRef Shirmohammadi Z, Mozafari F, Miremadi S-G (2017) An efficient numerical-based crosstalk avoidance codec design for nocs. Microprocess Microsyst 50:127–137CrossRef
23.
go back to reference Shirmohammadi Z (2019) Op-fibo: an efficient forbidden pattern free CAC design. Integration 65:104–109CrossRef Shirmohammadi Z (2019) Op-fibo: an efficient forbidden pattern free CAC design. Integration 65:104–109CrossRef
24.
go back to reference Shirmohammadi Z, Mahdavi Z (2018) An efficient and low power one-lambda crosstalk avoidance code design for network on chips. Microprocess Microsyst 63:36–45CrossRef Shirmohammadi Z, Mahdavi Z (2018) An efficient and low power one-lambda crosstalk avoidance code design for network on chips. Microprocess Microsyst 63:36–45CrossRef
25.
go back to reference Lakshmi KASS, Keerthi A, Sri KM, Vinodhini M (2020) Code with crosstalk avoidance and error correction for network on chip interconnects. In: 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI) (48184). IEEE, pp 75–79 Lakshmi KASS, Keerthi A, Sri KM, Vinodhini M (2020) Code with crosstalk avoidance and error correction for network on chip interconnects. In: 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI) (48184). IEEE, pp 75–79
Metadata
Title
ST-CAC: a low-cost crosstalk avoidance coding mechanism based on three-valued numerical system
Authors
Zahra Shirmohammadi
Ata Khorami
Martin Eugenio Omana
Publication date
02-01-2021
Publisher
Springer US
Published in
The Journal of Supercomputing / Issue 7/2021
Print ISSN: 0920-8542
Electronic ISSN: 1573-0484
DOI
https://doi.org/10.1007/s11227-020-03527-0

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