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Static Analysis for Hardware Design

  • 2026
  • OriginalPaper
  • Chapter
Published in:
Authors
Mads Rosendahl
Maja H. Kirkeby
Published in
Languages, Compilers, Analysis - From Beautiful Theory to Useful Practice
Publisher
Springer Nature Switzerland

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Abstract

This chapter explores the application of classical data flow analyses in hardware design, focusing on the challenges of converting algorithms for traditional architectures into highly parallel circuits. It discusses the potential of high-level synthesis tools and the need for further exploration to fully exploit the potential of high-level parallelism. The chapter introduces a subset of the hardware description language Chisel, which is well-suited for algorithm realization. It provides a formal semantics for this subset and establishes a framework for constructing data flow analysis. The analysis is meant to be used in the development phase to give information on possible flows and values to locate inefficiencies or unintended behaviors of the design. The chapter also discusses potential extensions to the analysis and ways to improve its precision. It concludes with a discussion of related works and the potential for future research in this area.
AI Generated

This summary of the content was generated with the help of AI.

To Alan Mycroft.
Ph.D. supervisor and Ph.D. supervisor’s supervisor.
This work is supported by the Independent Research Fund Denmark Project no. 2102-00281B.

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previous chapter On Graded Coeffect Types for Information-Flow Control
next chapter Context-Aware Air Quality Analytics Using Low-Cost Sensors and First-Order Logic
Title
Static Analysis for Hardware Design
Authors
Mads Rosendahl
Maja H. Kirkeby
Copyright Year
2026
Book
Languages, Compilers, Analysis - From Beautiful Theory to Useful Practice

Print ISBN: 978-3-032-08186-5

Electronic ISBN: 978-3-032-08187-2

Copyright Year: 2026

DOI
https://doi.org/10.1007/978-3-032-08187-2_8
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