Study and Analysis of Low Power Dynamic Comparator

Nowadays, everything will be digital for ease of processing, but the real world is in analog. Various techniques has been used to convert the analog signal to digital, and the fastest analog-to-digital converter (ADC) is Flash type ADC among all. It requires a high-speed comparator, which compares the analog input signals and produces the digital output through a predetermined threshold voltage accordingly. However, high-speed comparator increases the transistor and hence correspondingly increases large area, supply voltage, power, etc. Also, the system with low power dissipation speeds reduction for many transistors with a high offset voltage. Therefore, designing an ADC system that requires less power with faster operation is a great concern. Diverse kinds of comparators are available in the present scenario. In this paper, it has analyzed Conventional dynamic comparator, Double tail dynamic comparator, Doubletail comparator with enhanced latch regeneration and proposed comparator. The projected comparator with enhanced latch regeneration speed is better than the previous two conventional dynamic comparators in terms of power and speed.