10. Synthesis Optimization Using VHDL

The PLD-based designs can be described by using concurrent and sequential VHDL constructs. In the practical scenario, the objective is to describe the design functionality by using synthesizable VHDL constructs and that can be accomplished by using important combinational and sequential design guidelines. This chapter focuses on the designs such as ALU, parity checkers, generators, memories, multipliers, and barrel shifters. This chapter also discusses about the synthesis result with the data path and control paths. The synthesis optimization techniques are discussed for the better synthesis outcome and used during RTL design cycle. This chapter is useful for ASIC and FPGA designers to understand the design using VHDL, critical paths and optimizations, and registered inputs and outputs. Even this chapter discusses about the synthesis outcome using Altera and Xilinx PLDs.