The g m /I D Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits

Sizing methods assessing drain currents and gate widths of a simple circuit are reviewed in this chapter. The circuit, shown in Fig. 1.1, consists of a saturated common source transistor loaded by a capacitor. A constant current source is feeding the drain. The circuit is called currently the ‘Intrinsic Gain Stage’ (I.G.S.), the name ‘intrinsic’ underlining the fact that few parts aside the transistor control the performances of the circuit.

Our objective is to find gate widths and drain currents enabling to achieve a prescribed gain-bandwidth product ω _T . We therefore consider the small signal equivalent circuitshown in Fig. 1.2. The input is an open circuit while the output consists of a dependent current source g _m v _in (where g _m represents the transconductance of Q) in parallel with the output conductance g _d and the capacitor C.

We review in this chapter the main attributes of the ‘Charge Sheet Model’ (C.S.M.) introduced by J.R. Brews in 1978 (Brews 1978; Van de Wiele 1979). Although its name contains the word ‘Model’, the C.S.M is not a design tool. It is an invaluable means however for understanding some of the mechanisms governing current in MOS transistors for it scrutenizes phenomena otherwise difficult to apprehend. Unfortunately, the C.S.M. concerns only long channel MOS transistors implemented in a uniformly doped substrate (gradual channel approximation). Trying to predict drain currents of real transistors with the C.S.M. does not work.

Figure 2.1 depicts the structure of the NMOS transistor considered throughout this chapter. The two vertical lines without any other demarcation called respectively S and D symbolize the source and drain junctions. Two-dimensional effects are ignored, obliterating consequently items such as channel length modulation, Drain Induced Barrier Lowering (DIBL), etc. The source, drain and gate voltages are called respectively V _S , V _D and V _G , the surface potential ψ _S and the non-equilibrium voltage V. The latter, called also the channel voltage, varies from V _S at the source to V _D at the drain. Single indices relate to voltages defined with respect to the substrate. Double indices relate to voltages defined with respect to references other than the substrate. For instance, V _GS is the voltage difference between the gate and the source.

An interesting representation of the drain current can be obtained when the expression below is used for the drain current (Tsividis 1999): The equation is derived from, the proportionality of the minority carrier density to the exponential function acknowledged by Boltzmann statistics:

The basic E.K.V. model considered in the previous chapter is not suited for real transistors for it makes use of the “gradual channel” approximation, like the C.S.M. Non-uniform doping, mobility degradation, short channel effects, etc. are ignored. Advanced models like BSIM and PSP, which are primarily circuit simulation tools, take care of these but don’t offer the degree of flexibility that is desirable.

We show in this chapter that as long as the source and drain voltages with respect to the substrate remain constant, DC currents, g _m ∕ I _D and g _d ∕ I _D ratios of real transistors, even sub-micron devices, can be reconstructed by means of the basic E.K.V model. Once V _S or V _D is modified, the parameters must be updated. The model remains unchanged however.

In Chapter 1, the Intrinsic Gain Stage was sized in strong and weak inversion and, in Chapter 4, in moderate inversion. Only gradual channel models were utilized. The extension of the E.K.V model to short channel devices considered in Chapter 5 paves the way towards the sizing of real Intrinsic Gain Stages.

In the common gate configuration, the gate-to-source and the drain-to-source voltages, V _GS and V _DS , vary with the source-to-substrate voltage V _S . As a result, the compact model parameters require continuing updating.

Figure 7.1 displays the drain current versus the source voltage V _S of the 100 nm N-channel transistor considered in the previous chapter taking advantage of updated n, V _To and I _Suo parameters. The gate- and drain-to-substrate voltages are constant and respectively equal to 0.9 and 1.0 V. The currents predicted by the compact model with and without mobility degradation are represented respectively by the continuous and dashed curves. Crosses represent the ‘semi-empirical’ drain current. When V _S is small, the impact of mobility degradation is considerable for the gate-to-source and drain-to-source voltages are large. As V _S increases, the two curves concur progressively until they merge in weak inversion giving birth to the distinctive weak inversion straight line.

Fixing currents and transistors widths of Op. Amps is a multifaceted task owing to the growing number of choices that can be made. Sizing implies hierarchy. Some objectives ought to be satisfied whichever choices. They shape the specifications list. A typical example is the I.G.S gain-bandwidth product. Other objectives are desirable but not mandatory. They determine attributes like power consumption versus area. Specifications determine the dimensions of the g _​m ∕ ​I _​D sizing spacewhile attributes delineate optimization areas within the sizing space. The specificationsof the Miller Op. Amp considered in this chapter are twofold: a prescribed gain-bandwidth product and an assessment regarding stability. The sizing space conforms to a two-dimensional space. Every point represents a distinct Miller Op. Amp that fulfills the same specifications. Low-power consumption demarcates a region within the 2D sizing space. Area minimization relates to another region. Eventually regions intersect easing choices. Whichever combination, specifications must be met anyway.

The axes of the sizing space play the same role as the gate voltage, drain current or normalized drain current in the I.G.S. They represent variables controlling the modes of operation of transistors or ensembles of transistors. In the Miller Op. Amp, we are going to focus on the two stages and control their behavior by means of two distinct vectors. Each vector is supposed to control transistors that have a strong impact on the fulfillment of the specifications.