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Journal of Computational Electronics

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11-03-2024

Three-dimensional quantum-corrected Monte Carlo device simulator of n-FinFETs

Authors: C. S. Soares, G. F. Furtado, A. C. J. Rossetto, G. I. Wirth, D. Vasileska

Published in: Journal of Computational Electronics | Issue 2/2024

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Abstract

The effective potential approach was successfully incorporated as a quantum correction to a Monte Carlo device simulator of n-FinFETs to take into account the electron quantum confinement. The electron line density calculated by the effective potential approach agrees very well with the one calculated by a 2D Schrödinger–Poisson solver. Next, the results for the drain current as a function of the gate and drain voltage obtained by the semiclassical and by the quantum-corrected Monte Carlo device simulator were compared. The quantum-corrected Monte Carlo device simulator properly models volume inversion, which reduces the impact of surface roughness scattering, thus improving the electron drift velocity. Additionally, the quantum correction allows the modeling of the reduction of electron density in the n-FinFETs channel due to the quantum-mechanical size quantization effect. This, in turn, leads to a reduction of the drain current.

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Title: Three-dimensional quantum-corrected Monte Carlo device simulator of n-FinFETs
Authors: C. S. Soares
G. F. Furtado
A. C. J. Rossetto
G. I. Wirth
D. Vasileska
Publication date: 11-03-2024
Publisher: Springer US
Published in: Journal of Computational Electronics / Issue 2/2024
Print ISSN: 1569-8025
Electronic ISSN: 1572-8137
DOI: https://doi.org/10.1007/s10825-024-02145-w

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Springer Professional "Wirtschaft+Technik"

Springer Professional "Technik"

Springer Professional "Wirtschaft"

Numerical analysis and performance study of a double-heterojunction GaAs-based solar cell

Novel analytical STFT expressions for nonlinear power engineering problem solving

Oscillations of transverse magnetoresistance in the conduction band of quantum wells at different temperatures and magnetic fields

Simulation of avalanche time in thin GaN/4H–SiC heterojunction avalanche photodiodes

Numerical investigation of energy level strategy for TMO/Si tunneling heterojunction solar cells

Triple-metal gate work function engineering to improve the performance of junctionless cylindrical gate-all-around Si nanowire MOSFETs for the upcoming sub-3-nm technology node