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2013 | Book

Introduction Read chapter Read first chapter

Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits

Author: Martin Wirnshofer

Publisher: Springer Netherlands

Book Series : Springer Series in Advanced Microelectronics

Part of: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik" , Springer Professional "Wirtschaft"

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About this book

Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted “on the fly” by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engineers interested in adaptive techniques for low-power CMOS circuits.

Table of Contents

Frontmatter
Chapter 1. Introduction
Abstract
Driven by Moore’s Law, the transistor count per microchip has doubled approximately every two years for the last decades. In combination with the increase in transistor speed, the performance and functionality in solid-state circuits has improved continuously. On the other hand, this growth has made power consumption a major design criterion in digital circuits. Especially in portable devices like smart-phones or tablets, the demand for increasing performance with the constraints of a very limited power source makes power efficient circuits indispensable. Considering these facts, the term performance per watt is gaining importance for design companies, device manufacturers as well as customers.
Martin Wirnshofer
Chapter 2. Sources of Variation
Abstract
Variations in process, supply voltage and temperature (PVT) have always been an issue in Integrated Circuit (IC) Design. In digital circuits, PVT fluctuations affect the switching speed of the transistors and thus the timing of the logic. To guarantee fault-free operation for a specified clock frequency, IC designers have to quantify these uncertainties and account for them adequately. This is typically done by guard-banding, i.e. adding sufficient voltage safety margin to ensure proper working even under worst-case condition.
At recent technology nodes, transistor characteristics are more and more influenced also by aging effects. These wear-out effects, namely hot carrier injection (HCI) and bias temperature instability (BTI), degrade the drive current of transistors during use. Hence, further safety margin has to be added, dependent on the specified lifetime of a product.
The following four sections will give an overview of process, voltage and temperature variations as well as aging (PVTA). The necessary fundamentals are briefly explained and the impact on circuit-level timing is discussed.
Martin Wirnshofer
Chapter 3. Related Work
Abstract
As discussed in the previous chapter, process, voltage and temperature variations as well as aging significantly affect the timing of digital circuits. To cope with these uncertainties, worst-case guard-banding is still the most common design approach. As the worst-case is very rare however, in most cases power or performance is wasted by this approach.
By scaling the operating voltage, energy efficiency can be increased. Tuning the supply voltage dependent on PVTA variations is referred to as adaptive voltage scaling (AVS). The term AVS is often interchanged with dynamic voltage scaling (DVS), but note that DVS considers only varying workloads and does not adapt to PVTA variations at all. To clarify the difference between both techniques, they are explained in the following two sections.
Martin Wirnshofer
Chapter 4. Adaptive Voltage Scaling by In-situ Delay Monitoring
Abstract
In the Pre-Error AVS scheme the timing information is provided by in-situ delay monitors (Pre-Error flip-flops), that detect late but still non-erroneous data transitions in critical paths. Late data transitions are defined by the pre-error detection window, i.e. a defined time interval T pre before the triggering edge of the clock.
The timing of digital circuits is influenced by PVTA variations and so is the frequency of pre-errors. The pre-error rate, indicating the timing slack, is thus used to adapt the supply voltage on-the-fly/on-line, i.e. during normal circuit operation. During each N clock cycles, forming an observation interval, the number of pre-errors n pre is counted and it is decided whether to change the voltage subsequently. For a pre-error count n pre under a lower threshold n limit↓, the voltage is decreased by ΔV DD . If the count is above the upper limit n limit↑, the voltage will be increased by ΔV DD . For counts inside the limits the voltage is maintained.
Martin Wirnshofer
Chapter 5. Design of In-situ Delay Monitors
Abstract
The in-situ delay monitors used for our AVS approach are conventional flip-flops with additional circuitry to detect pre-errors (late data transitions). Therefore, we refer to these in-situ delay monitors also as Pre-Error flip-flops. Besides pre-error detection, these flip-flops are also capable of detecting early transitions in order to observe the activity rate of the circuit. Note that early transitions are transitions that occur before the pre-error detection window.
For realizing the pre-error detection window, either the duty-cycle of the clock signal or a delay element can be used. In this chapter three different designs to implement the Pre-Error flip-flop are discussed in detail. In the first design, called Crystal-ball flip-flop, a delay element comprising an inverter chain defines the pre-error detection window. In the other two designs, the duty-cycle of the clock signal is exploited as the detection window.
Martin Wirnshofer
Chapter 6. Modeling the AVS Control Loop
Abstract
Adapting the supply voltage by using in-situ delay monitors forms a closed-loop control system. The last chapter focused on the in-situ delay monitors (Pre-Error flip-flops) acting as sensors of this system. The following chapter will now deal with the entire control loop. First, we show how the whole system can be analyzed accurately and at the same time efficiently. Subsequently, the Markov chain, which is used to model the AVS system, is explained thoroughly. Describing the voltage adaptation by a Markov model is a beneficial approach, which can be used to evaluate the power saving potential and reliability of the Pre-Error AVS system. In the last section of the chapter, the stability of the AVS control loop is discussed, which has to be ensured for proper system operation.
Martin Wirnshofer
Chapter 7. Evaluation of the Pre-Error AVS Approach
Abstract
To evaluate the power saving potential of the Pre-Error AVS technique we use the Markov chain model, described in the previous chapter. The Markov chain describes the switching between the discrete output levels of the voltage regulator and thus represents the whole control system. With this model, the resulting probabilities of being at the individual voltage levels can be determined very fast. Moreover, the effect of global as well as local variations on the voltage control can be analyzed very accurately and efficiently. In the following we will also cover the power overhead introduced by the necessary AVS circuitry consisting of the Pre-Error flip-flops and the AVS control unit. As a proof of concept, the application of Pre-Error AVS to an image processing circuit is finally shown.
Martin Wirnshofer
Chapter 8. Conclusion
Abstract
To boost the power efficiency of digital CMOS circuits, a novel Adaptive Voltage Scaling (AVS) approach is proposed, which is capable of handling the increasing PVT variations as well as aging effects in integrated circuits. This Pre-Error AVS approach reduces unnecessary voltage safety margin by adapting the supply voltage to the actual operating condition of a chip and thereby optimizes power consumption.
Martin Wirnshofer
Backmatter
Metadata
Title
Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits
Author
Martin Wirnshofer
Copyright Year
2013
Publisher
Springer Netherlands
Electronic ISBN
978-94-007-6196-4
Print ISBN
978-94-007-6195-7
DOI
https://doi.org/10.1007/978-94-007-6196-4