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The Journal of Supercomputing

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03-07-2018

VLSI architecture of binary encoding technique for fast motion estimation based on Hamming distances

Authors: A. Arun, M. Devaraju

Published in: The Journal of Supercomputing | Issue 6/2020

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Abstract

One-bit and two-bit transforms-based block motion estimation methods are introduced to reduce the computational complexity of the ME procedure by assisting a modest Boolean XOR operation, matched with lower bit-depth illustrations of image frames. However, due to some computational complexity and failure to develop the mathematical expression at the hardware level, a binary encoding mapping function technique is proposed. The mathematical expressions for the proposed method are easy to design and develop in hardware. The architecture of the proposed method is developed in Verilog HDL and implemented in Xilinx Artix-7. The results of the proposed method are checked for area, power and maximum frequency levels in different types of video frames.

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Title: VLSI architecture of binary encoding technique for fast motion estimation based on Hamming distances
Authors: A. Arun
M. Devaraju
Publication date: 03-07-2018
Publisher: Springer US
Published in: The Journal of Supercomputing / Issue 6/2020
Print ISSN: 0920-8542
Electronic ISSN: 1573-0484
DOI: https://doi.org/10.1007/s11227-018-2468-5

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