VLSI Implementation of PN Sequence Generator Using Two Different Multiplication Algorithms

Wireless communication system plays an essential role in data transmission system. In wireless systems like satellite network, mobile communication, or any data transmitted network, a specified band is allotted. Such network has its own specified allotted spectrum for secure communication. Safe data transmission and reception are important and difficult tasks. Such data transmission needs some secure techniques to transmit data securely, and one such technique is hiding the transmission data or hiding the message signals. To provide security to message signal, random noise is added through pseudo-noise (PN) sequence generator. When PN sequence is added to a message signal, it resembles like a noise making it hard to decode and increases the signal bandwidth to utilize the whole spectrum. In this paper, the approach to generate PN sequence using Vedic multiplier has been proposed. In a Vedic multiplier, multiplication is done by using Urdhva Tiryagbhyam sutra, and basic multiplication method is used to design conventional multiplier. The PN sequence generator is implemented using Verilog HDL. The comparative analysis of Vedic multiplier over the conventional multiplier is implemented using Altera FPGA. Vedic multiplication gives an effective result when compared to conventional multipliers.