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2014 | OriginalPaper | Buchkapitel

3. Energy-Efficient Design Techniques

verfasst von : Rong Ye, Qiang Xu

Erschienen in: Energy-Efficient Fault-Tolerant Systems

Verlag: Springer New York

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Abstract

While the relentless scaling of CMOS technology has brought digital IC designs with enhanced functionality and improved performance in every new generation, at the same time, the associated ever-increasing on-chip power and temperature densities make them suffer from more severe reliability threats [6, 93]. For example, as demonstrated in [94], the average mean-time-to-failure (MTTF) of a contemporary superscalar processor drops by about 4 ×from 180 to 65 nm technology node. In fact, the failure rates for today’s electrical systems can be quite high, e.g., as high as 16.4 % for the Microsoft Xbox 360 within 10 months [90].

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Fußnoten
1
The mode execution probabilities can be estimated as in [81].
 
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Metadaten
Titel
Energy-Efficient Design Techniques
verfasst von
Rong Ye
Qiang Xu
Copyright-Jahr
2014
Verlag
Springer New York
DOI
https://doi.org/10.1007/978-1-4614-4193-9_3

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