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Erschienen in:

01.06.2015

Energy reduction in 3D NoCs through communication optimization

verfasst von: Ozcan Ozturk, Ismail Akturk, Ismail Kadayif, Suleyman Tosun

Erschienen in: Computing | Ausgabe 6/2015

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Abstract

Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. Specifically, on a heterogeneous 3D NoC architecture, we explore how different types of processors can be optimally placed to minimize data access costs. Moreover, we select the optimal set of links with optimal voltage levels. The experimental results indicate significant savings in energy consumption across a wide range of values of our major simulation parameters.

Vorheriger Artikel Using constraint programming for the design of network-on-chip architectures

Nächster Artikel System on chip failure rate assessment using the executable model of a system

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Titel: Energy reduction in 3D NoCs through communication optimization
verfasst von: Ozcan Ozturk
Ismail Akturk
Ismail Kadayif
Suleyman Tosun
Publikationsdatum: 01.06.2015
Verlag: Springer Vienna
Erschienen in: Computing / Ausgabe 6/2015
Print ISSN: 0010-485X
Elektronische ISSN: 1436-5057
DOI: https://doi.org/10.1007/s00607-013-0378-1

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