Weitere Kapitel dieses Buchs durch Wischen aufrufen
In a scenario where the complexity and diversity of embedded systems is rising and causing extra pressure in the demand for performance at the lowest possible power budget, designers face the challenge brought by the power and memory walls in the production of embedded platforms. The focus of the ERA project is to investigate and propose new methodologies in both tools and hardware design to break through these walls, and help design the next-generation embedded systems platforms. The proposed strategy is to utilize adaptive hardware to provide the highest possible performance with limited power budgets. The envisioned adaptive platform employs a structured design approach that allows integration of varying computing elements, networking elements, and memory elements. For computing elements, ERA utilizes a mixture of commercially available off-the-shelf processor cores, industry-owned IP cores, and application-specific/dedicated cores. These are dynamically adapted regarding their composition, organization, and even instruction-set architectures, to provide the best possible performance/power trade-offs. Similarly, the choice of the most-suited network elements and topology and the adaptation of the hierarchy and organization of the memory elements can be determined at design-time or at run-time. Furthermore, the envisioned adaptive platform must be supported by and/or made visible to the application(s), run-time system, operating system, and compiler, exploiting the synergism between software and hardware. Having the complete freedom to flexibly tune the hardware elements allows for a much higher level of efficiency, riding the trade-off curve between performance and power compared to the state of the art. An additional goal of the adaptive platform is to serve as a quick prototyping platform in embedded systems design.
Bitte loggen Sie sich ein, um Zugang zu diesem Inhalt zu erhalten
Sie möchten Zugang zu diesem Inhalt erhalten? Dann informieren Sie sich jetzt über unsere Produkte:
Bhavishya Goel, Sally A. McKee, Roberto Gioiosa, Karan Singh, Major Bhadauria, Marco Cesati, “Portable, scalable, per-core power estimation for intelligent resource management,” Greencomp, International Conference on Green Computing, pp.135–146, 2010.
M. Alioto, P. Bennati, R. Giorgi “Exploiting locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed”, In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 37–40, May 2010.
G. Hamerly, E. Perelman, J. Lau, B. Calder, “Simpoint 3.0: Faster and more flexible program phase analysis”, In Journal of Instruction Level Parallelism, vol 7, 2005.
N. Puzović, S. A. McKee, R. Eres, A. Zaks, P. Gai, S. Wong, R. Giorgi, “A Multi-Pronged Approach to Benchmark Characterization” in IEEE International Conference on Cluster Computing Workshops and Posters (CLUSTER WORKSHOPS), pp.1–4, 2010.
C. Zeferino, A. Susin, “SoCIN: A Parametric and Scalable Network-on-Chip” in 17th Symposium on Integrated Circuits and System (SBCCI), 2003, pp. 169–174.
Bertozzi, D. et al., “NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip”, IEEE Transaction on Parallel and Distributed System, 2005, pp. 113–129.
K. Srinivasan and K. S. Chatha, “A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures,” in Proceedings of Design, Automation and Test in Europe Conf.,vol. 1, 2006, pp. 1–6. CrossRef
J. Andrews, N. Baker, “Xbox 360 System Architecture”, IEEE Micro, vol. 26, no. 2, 2006, pp. 25–37. CrossRef
Goldstein S. C., Schmit H., Budiu M., Cadambi S., Moe M., and Taylor R. R., “PipeRench: A Reconfigurable Architecture and Compiler”. Computer 33, 4, 70–77, 2000. CrossRef
Vassiliadis S., Wong S., Gaydadjiev G., Bertels K., Kuzmanov G., and Panainte E.M., “The MOLEN Polymorphic Processor”. IEEE Transactions on Computers, 53, 11, 1363–1375, 2004. CrossRef
Hauser J. R., and Wawrzynek, J., “Garp: a MIPS Processor with a Reconfigurable Coprocessor”. In Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM), 1997.
Waingold E., Taylor M., Srikrishna D., Sarkar V., Lee W., Lee V., Kim J., Frank M., Finch P., Barua R., Babb J., Amarasinghe S., and Agarwal A., ”Baring It All to Software: Raw Machines”. Computer 30, 9, 86–93, 1997. CrossRef
Lysecky R., Stitt G., Vahid F., “Warp Processors”. In ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 659–681, 2006.
Clark, N., Kudlur, M., Park, H. Mahlke, S., Flautner, K., “Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization”. In International Symposium on Microarchitecture (MICRO-37), pp. 30–40, Dec. 2004.
Beck A.C.S., Rutzig Mateus B., Gaydadjiev G., Carro, L., “Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications,” in Proceedings of the Design, Automation and Test Conference (DATE), pp.1208-1213, 2008.
D.H. Albonesi, “Dynamic IPC/clock rate optimization,” in Proceedings of the 25th International Symposium on Computer Architecture (ISCA-25), 1998.
D.H. Albonesi, “Selective Cache Ways: On-demand Cache Resource Allocation”, in Proceedings 32nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-32), pp. 248–259, 1999.
S. Dropsho, et.al., “Integrating adaptive on-chip storage structures for reduced dynamic power,” in Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2002.
M. Zhang and K. Asanovi’c, “Highly Associative Caches for Low-power Processors”, Kool Chips Workshop, 33 rd International Symposium on Microarchitecture, 2000.
S. Kaxiras and M. Martonosi, “Architectural Techniques for Low Power”, Morgan & Claypool Publishers, 2008.
S. Kaxiras, Z. Hu, and M. Martonosi, “Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power”, in Proceedings of 28th International Symposium on Computer Architecture (ISCA-28), 2001.
- ERA – Embedded Reconfigurable Architectures
Debora Motta Matos
Sally A. Mckee
- Springer New York
- Chapter 10