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2017 | CompoundObjectErratum | Buchkapitel

Erratum to: PLD Based Design with VHDL

verfasst von : Vaibbhav Taraate

Erschienen in: PLD Based Design with VHDL

Verlag: Springer Singapore

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Excerpt

The original version of the book was inadvertently published without the following corrections:
1.
In Front matter, p. viii, Preface: explanation for Chaps. 9 and 10 are modified as per TOC.
 
2.
In Chap. 1, p. 2, sixth line of second paragraph in Sect. 1.1: “Very-High-Speed Integrate Circuit Hardware Description Language (V HSIC HDL)” has been modified to “V HSIC HDL: Very High Speed Integrated Circuit Hardware Description Language”.
 
3.
In Chap. 1, p. 16, last line: “end struct;” is changed to “end arch_struct;” in program “Example 1.1 Structural style for the half adder”; p. 17, the last line: “end behav;” is changed to “end arch_behav;” in program “Example 1.2 Behavior style of the VHDL code for half adder”.
 
4.
In Chap. 2, p. 28 and p. 30: “Example 2.2 Synthesizable VHDL code for two-input OR logic” and “Example 2.3 Synthesizable VHDL code for NOR logic” are replaced with the new programing codes, respectively.
 
5.
In Chap. 4, p. 100: “Example 4.6 Synthesizable RTL for binary-to-excess-3 code converter” is replaced with the new programming code; the typo error in cross links for “Examples 4.13, 4.14, 4.16, and 4.18” are changed to “Examples 4.12, 4.13, 4.14 and 4.15” respectively.
 
6.
In Chap. 7, p. 227: “if(clk= ‘1’ and clk’event ) then” is updated with “if(clk= ‘0’ and clk’event ) then”.
 
7.
In Chap. 8, p. 250, Example 8.8: the condition “when “1100” => y_out <= “00010”” is updated with “when “1100” => y_out <= “0001000000000000””.
 
8.
In Chap. 9, p. 277, Table 9.1: s6 state value for binary encoding “101” is updated with “110”.
 
9.
In Chap. 10, p. 333: “Example 10.3 VHDL RTL for the arithmetic unit” is updated with new programing code.
 
10.
The cover type is changed from “Soft Cover” to “Hard Cover”.
 
The erratum chapters and the book have been updated with the changes. …

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Metadaten
Titel
Erratum to: PLD Based Design with VHDL
verfasst von
Vaibbhav Taraate
Copyright-Jahr
2017
Verlag
Springer Singapore
DOI
https://doi.org/10.1007/978-981-10-3296-7_12

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