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Über dieses Buch

This book provides readers with a comprehensive review of the state of the art in error control for Network on Chip (NOC) links. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

On-chip interconnects play an important role for the performance of current VLSI system. As technology scales into nanoscale regime, interconnect is facing several design challenges in terms of delay, power and reliability [1–3].
Bo Fu, Paul Ampadu

Chapter 2. Solutions to Improve the Reliability of On-Chip Interconnects

Various noise reduction and error control techniques have been applied to improve the reliability of on-chip interconnects. Noise reduction techniques include increasing wire width and spacing [1, 2], shielding [3–7], repeater insertion [8–13], crosstalk avoidance codes [14–18], skewed transition [19–25] and decoupling capacitors [26–28]. Error control techniques improve the reliability of on-chip interconnect by correcting errors using retransmission, error control codes and spare wires. The use of these techniques relaxes the reliability requirements of circuit components reducing the cost of manufacturing, verification, and testing. In this chapter, we will review both noise reduction and error control techniques and their pros and cons.
Bo Fu, Paul Ampadu

Chapter 3. Networks-on-Chip (NoC)

The move to many-core system is expected to become the dominant trend in the near future. With technology scaling into nanoscale regime, hundreds and even thousands of intellectual property (IP) cores can be integrated into a single chip. How to provide efficient and reliable communication between these IP cores becomes a bit problem. The conventional bus-based infrastructures are no longer sufficient to handle intensive on-chip communication. Network-on-chip (NoC) is emerging as an efficient solution to solve the aggravating scalability and bandwidth issues of on-chip communication by replacing traditional bus structures with a packet-switched network. This chapter is developed to introduce the common NoC architectures and the reliability issues facing in NoC design.
Bo Fu, Paul Ampadu

Chapter 4. Error Control Coding for On-Chip Interconnects

Error control codes (ECCs) have been widely applied in communication systems [1]. In ECCs, parity check bits are calculated based on the input data. The input data and parity check bits are transmitted across a noisy channel. In the receiver, an ECC decoder is used to detect or correct the errors induced during the transmission. A powerful ECC usually requires more redundant bits and more complex encoding and decoding processes, which increases the codec overhead. To meet the tight speed, area, and energy constraints imposed by on-chip interconnect links, ECCs used for on-chip interconnects need to balance reliability and performance. In this chapter, we will first introduce the basic concepts of error control coding. Then, the error control codes used for on-chip interconnect and their hardware implementations are discussed.
Bo Fu, Paul Ampadu

Chapter 5. Energy Efficient Error Control Implementation

Error control is applied to improve the reliability of on-chip communication. However, on-chip interconnects are still facing the challenge of the increased energy consumption. It is important to consider energy efficiency in error control realization. In this chapter, we will introduce design techniques, which can efficiently balance the energy efficiency and reliability of on-chip interconnects.
Bo Fu, Paul Ampadu

Chapter 6. Combining Error Control Codes with Crosstalk Reduction

Conventional error control codes (ECCs) has been successfully applied to improve the reliability of on-chip interconnect by correcting logic errors. Unfortunately, ECCs is inefficient to address crosstalk-induced delay uncertainty, which greatly decreases the system performance even causing timing errors. Crosstalk-induced delay uncertainty results from the dependence of coupling capacitance and inductance on different wire switching patterns. In this chapter, we mainly focus on the delay uncertainty caused by the capacitive crosstalk coupling. The capacitive crosstalk induced delay uncertainty can be alleviated by techniques such as shielding, routing, wire sizing and spacing, crosstalk avoidance codes (CACs), skewed transitions, and staggered repeater. Typically, these methods do not address logic errors. In this chapter, we will discuss the solutions, which efficiently address both logic errors and capacitive crosstalk induced delay uncertainty simultaneously.
Bo Fu, Paul Ampadu

Backmatter

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