Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects

To study the effects of SEUs, an initial FinFET SRAM 3D model was developed using Sentaurus™ TCAD. In comparison to SPICE simulations, this tool allows larger flexibility while controlling the device physics aspects, including the impact location of ionizing particles and its associated LET. This study considers three models of FinFET-based SRAM cells: High-Density (HD), High Performance (HP), and Low Voltage (LV). Because of the discrete nature of fins, it is not possible to tune the transistor parameters to obtain an ideal robustness/area ratio as it would be feasible in planar CMOS. Therefore, each model has its configuration with a different distribution of fins in the cell’s transistors. The SRAM cell structure is divided into three parts with their proper notation (PU:PG:PD), meaning respectively: Pull Up, Pass Gate and Pull Down [18]. As an example, the HD configuration adopts a (1:1:1) configuration, meaning that all the cell transistors are composed of a single fin.

Figure 2 shows the simulation flow adopted in the Synopsys Sentaurus™ environment [20]. Firstly, the physical process of cells was developed, using the Sentaurus™ Process (S_Process) tool. The transistors designed with the Sentaurus™ tool were calibrated using the physical characteristics described by the 2015 International Technology Roadmap for Semiconductors (ITRS) [21], summarized in Table 1. The mesh grid configured in these simulations was generated given special attention to the active zones such as channel, source, and drain.

Using the Sentaurus Device (S_Device), the operational parameters of the circuit are implemented, allowing its validation. The curve of Static Noise Margin (SNM) was also collected at this stage in order to properly evaluate the reliability of the circuit with respect to noise fluctuations. After these steps, the injected ionizing particle is modeled, using the same tool. The tool Sentaurus Visual (S_Visual) was used to analyze the electrical behavior, by wave verification. Finally, the Inspect tool was used to verify the transient operations while simulating the ion impact.

The heavy-ion injection in TCAD simulation follows the methodology presented in [14], considering a Gaussian charge distribution with a track radius of 10 nm. To model the worst-case scenario of such particle strike, the charge track length should be longer than the fin height, with normal incidence over the drain of the sensitive transistor (off-state transistor). The sensitive transistor is the pull-down transistor when the node (inverter output) is charged with a logic ‘1’, or the pull-up transistor when the node is ‘0’.

In the simulation setup, the input parameters for heavy ions are given in charge per track length (pC/µm). To convert this value into the LET parameter the relation of 1 pC/µm is equivalent to a 97 MeV-cm²/mg LET in silicon [15]. For example, the alpha particles due to radioactive contamination in the packaging material can result in 0.015 pC/µm, which approximates 1.5 MeV-cm²/mg [15]. This analysis aims to find the threshold LET that causes a bit-flip in the cell. Considering this LET, the drain current in the affected transistor is evaluated, obtaining important parameters, such as the collected charge (Q_coll), current peak (I_peak), pulse width, and general shape, which is then compared with the traditional double exponential. The obtained current shape is modeled in SPICE to allow transient injections and resistive defect modeling at the same time. This analysis is carried out in SPICE since TCAD simulations would demand a huge computational effort. The overall simulation flow, including the resistive defects modeling in SPICE, is depicted in Fig. 2.

The electrical simulations to evaluate the robustness of a FinFET-based SRAM cell in the presence of weak defects are performed using Hspice™ from Synopsys. The FinFET-based SRAM was designed using the Arizona State University’s 14 nm FinFET Predictive Technology Model (PTM) [22]. For this purpose, the injected charge to simulate single events in SPICE is set with a value lower than the excess charge observed when simulating a particle strike with LET = LET_th, while simultaneously injecting resistive defects. In this case, the defect resistance values are varied using an automated tool that interacts with the SPICE simulator. Note that the critical resistance (R_crit) is the defect resistance threshold that results in a bit-flip when injecting the ionizing particle. The methodology for resistive defects injection, according to the model shown in Fig. 1, is the same used in [7] and [22]. This effort is necessary to observe if resistive defects may change the cell’s robustness to SEUs. The opposite situation was also verified, simulating an event depositing the critical charge (Q_crit) at the same time that resistive defects are injected, in order to determine if SEEs are attenuated due to the presence of a given defect.

As previously mentioned, a FinFET-based SRAM cell was implemented based on the physical parameters described on the 2015 ITRS [21], and as presented in [19]. Three different models were adopted, whose configurations (number of fins of the transistors), along with the corresponding area, are shown in Table 2. As an example, Fig. 3 shows an LV SRAM cell modeled in 3D-TCAD. Different from this exemplary cell, the HD configuration, the most compact, would not possess a fin column on each side of the cell, and the HP configuration would show two fins in the PG. To reproduce industrial devices, only HD and LV cells use source and drain regions with a polyhedron of silicon over the fin [19]. Note that these structures do not cause a considerable current variation in the transistor when compared with the HP cell. Electrically, the LV model has a more robust SNM for a read operation, and the HP model is faster during reading and writing operations [19].

To validate the device’s electrical operation is compatible with the 14 nm node used as target technology, the electrical behavior was compared to the drain current/gate voltage data from the Arizona State University’s Predictive Technology Model (PTM) [22]. To observe the Id x Vg behavior, Fig. 4 presents the drain current (Id) comparison, for both p and n FinFETs considering two drain voltages, 0.05 V and 0.8 V. Table 3 shows the off and saturation currents (I_off and I_sat), as well as the percentage difference between the PTM model and the TCAD modeled device for each reported parameter. The I_off is obtained with 0.8 V as drain voltage and the I_sat with the highest possible voltage value. The normalized currents are the currents divided by the fin pitch in µm, thereby 0.042 for the developed transistor and 0.023 for PTM. Note that the difference between them is calculated using normalized values. Despite observing a significant difference between the saturation currents, the PTM model was used as a behavioral reference model only. The physical parameters of the PTM model are different from the parameters used in the TCAD model, consequently, the behavior is not expected to be exactly the same.

Table 4 summarizes the hold, read and write SNM values for the three different FinFET-SRAM cells developed using TCAD as well as for the circuit modeled according to PTM parameters in SPICE. Comparing the data, it is verified that the behavior of the circuit modeled in the TCAD simulator is correct, being even more robust than the PTM version. Finally, Fig. 5 shows the hold SNM butterfly curve of the FinFET-SRAM cell modeled using TCAD.

The heavy-ion simulation considers the particle strike in the corresponding time of 10 ps and the ion track according to the parameters presented in Section III. Considering that the cells were designed with a depth of 1 µm, the deep length for the ion track was set as 0.9 µm. Figure 6 depicts the cells’ behavior when an SEU is observed. In more detail, Fig. 6(a) presents the bit-flip caused by ionizing particles with the lower LETs (threshold LET, or LET_th) in the different designed cells, or, in other words, when Q_crit is achieved. However, according to [3], the definition of Q_crit in SRAMs is not as intuitive as for logic circuits, where it is associated exclusively with the charge stored in the node and the drive strength of the restoration transistors. In SRAMs, the feedback plays an important role, collaborating with the behavior of the transient current pulse. Two ways of defining Q_crit can be found in the literature. The first one considers the value of deposited or collected charge able to start bit-flips. The second definition considers the value of the charge flowing in excess during the transient current in the affected node, which considers also the charge flow due to the circuit dynamics (hence not merely the collected charge) [3]. Moreover, Fig. 6(b) shows the drain current observed for particles (with LET = LET_th) injected at one of the inverters’ nFET. One can notice a plateau region on the current pulses, corresponding to the occurrence of the feedback action. The feedback action tends to activate the nFET, which is nominally off before the transient. As can be observed from Fig. 6(a), the plateau happens while both transistors are simultaneously in a conduction state (near the inverter trip point). Since the n devices of LV and HP cells are built with two fins, the current on this plateau is higher, which facilitates the inversion of the bit stored in the cell. Thus, it can be expected that the LET_th for these two models is similar.

The data presented in Table 5 demonstrates that the HD cell is the most robust when considering transients injected in pull-down transistors; the LET_th obtained with TCAD simulations is higher. The table’s remaining columns show the charge that is injected to simulate the heavy-ion (Q_dep) and the excess charge (Q_exc), which is the charge disturbance on the affected node (integral of the transient current). Despite the lower LET_th, one may notice that Q_exc is higher for LV and HP cells due to circuit dynamics. Another point that deserves attention is that not all the deposited charge is collected, as already discussed by [3]. Indeed, related works often consider the quantity denominated Q_exc as the Q_crit in SPICE-based injection campaigns. However, it is clear that this may lead to an erroneous evaluation regarding the circuit reliability, especially for SRAMs, as can be observed in Table 5. According to [24], Q_crit values computed from currents of 3D device simulation are approximately 3 times smaller than those found using current models. Therefore, this paper uses the value of LET_th, based on the values obtained with TCAD, for reliability comparison purposes. Additionally, for SPICE simulations, we adopted the quantity Q_exc, which is the charge disturbance on the circuit due to the impact of a particle with LET = LET_th on the drain of the sensitive transistor. From here on, this work avoids using the term critical charge during its analysis, since smaller LET values and deposited charges may result in a higher amount of excess charge, as observed during TCAD simulations, and in Table 5.

The distance of the ion impact from the transistor drain and the track length also plays an important role. Figure 7 shows the drain current that results from the impact of a particle with LET = 80 MeV-cm² /mg occurring 112 nm from the drain region’s center of the pFET in the HD cell. The current difference observed in this figure is only caused by the variation of the charge track length from 150 to 200 nm. Integrating the results, one obtains a charge of 9.0 fC and 11 fC, respectively. It is possible to see that a much higher LET is needed to produce a similar amount of charge collection, able to generate a bit-flip if the impact occurs far from the drain.

The observed current curves in TCAD simulations were then modeled as current sources in SPICE. The well-established Messenger’s double exponential model [25] is still being applied in related works to simulate SEEs due to its simplicity, even for recent FinFET technologies [6]. However, in some cases, this model may not accurately represent the current behavior. For instance, in this work, the double exponential is suitable to model a particle with LET = LET_th striking the pull-down transistor of the HD cell because the current from the plateau has a low effect in the bit-flip, while the same is not true to the LV and HP cell (Fig. 6(b)). A previous work that investigated single events in FinFETs [6] considered the following values using the double exponential time constants for the execution of SPICE simulations: τ₁ = 2 ps and τ₂ = 20 ps (time constants of rising and falling exponentials, respectively). However, TCAD simulations in the present work showed that, for strikes on nFET of the HD configuration, the rising and fall times are similar, resulting in τ₁ = 6 ps, τ₂ = 9 ps, and (t_d2 – t_d1) = 7 ps (t_d1 and t_d2 are the initial times of both exponentials). Therefore, the double exponential curve is shown in Fig. 8(a) was used to perform transient injections on HD cells in SPICE, though varying the current peak according to the desired injected charge. Both curves (TCAD and SPICE modeled double exponential) are shown in Fig. 8(a).

However, the pulse shapes observed for the LV and HP configurations are significantly different from the double exponential. Hence, following the methodology proposed by [26], a combination of three exponential sources in SPICE is proposed to represent the behavior. The first is the double exponential with τ₁ = 6 ps, τ₂ = 8 ps, and (t_d2 – t_d1) = 7 ps with a short peak, the second source is a long double exponential with τ₁ = 6 ps, τ₂ = 100 ps, and (t_d2 – t_d1) = 80 ps. Finally, an exponential curve with a slow rising time constant completes the modeling, whit τ₁ = 85 ps, τ₂ = 8 ps, and (t_d2 – t_d1) = 80 ps. Figure 8(b) depicts these curves.

Although these three source models fit the observed transients very well, a further simplification may be executed. Figure 8(c) shows a comparison of curves with different particle LETs for LV cells, including a simulation in which no bit-flip has occurred. Based on these and other performed simulations, it was verified that besides the current’s peak value, the plateau amplitude and duration are the main parameters of the curve related to bit-flips. Therefore, the component of the later peak from the proposed curve can be removed to simplify the model, though keeping the plateau as shown in Fig. 8(b).

In order to evaluate the impact of SEUs on the reliability of the FinFET-SRAMs in the presence of resistive defects, simulations using Hspice™ were performed. A FinFET-SRAM cell adopting a 14 nm PTM technology was designed for simulating the ionizing particle as a current source in the pull-down transistor according to the models presented in the previous Section. The values of Q_exc corresponding to the transient effects (Q_{exc_nom}), the peak current (I_peak), and the plateau current (I_plateau) are summarized in Table 6. Note that the values of Q_{exc_nom} were obtained by integrating the current pulse, considering the lower values of I_peak that resulted in bit-flips in the SPICE model, and modeling the same value of plateaus observed in TCAD. This way, some variations in Q_{exc_nom} were observed when compared to the TCAD model. This difference is observed due to the fact that different technological parameters for the TCAD model and the SPICE PTM model are applied.

Table 7 shows the observed values of R_crit, along with the values of simulated Q_exc and the correspondent I_peak and I_plateau. The value of Q_{exc_alt} was reduced from Q_{exc_nom} by 10% to verify if weak defects can reduce the amount of charge needed to cause a bit-flip. For resistive open defects, the critical resistance is the lowest value that results in a bit-flip, considering the reduced value of Q_{exc_nom}. For resistive bridges, the R_crit are the highest values that render the cell susceptible to SEUs. The defects marked with ‘*’ indicate that this defect was injected into a different cell’s inverter than the transient was injected into.

Looking at Table 8, it is possible to observe that weak resistive defects may indeed modify the cell robustness. DFO2 and DFO4, which are low resistance open defects, as well as DFB2 and DFB6, which represent high resistances for bridge defects, represent this situation where the cell robustness is reduced. Note that the defect sizes adopted represent weak defects, which means that may not be detectable by manufacturing tests, even those able to detect dynamic faults, according to the results in [23].

This paper also investigated what is the nominal value of excess charge necessary for causing a bit-flip in a healthy cell. It was possible to observe that some defects may turn the cell more robust to the SEUs, as shown in Table 8. It is interesting to notice that some defects may have distinct impacts when occurring in the inverter that is affected by the SEU or during their occurrence in the opposite inverter. For example, if DFO2 occurs in the inverter hit by the ion, the bit-flip occurrence is facilitated, while, if it occurs in the opposite inverter, a higher collected charge is needed to turn the event into an SEU.