01.09.2014
Exploiting fine-grained parallelism in graph traversal algorithms via lock virtualization on multi-core architecture
Erschienen in: The Journal of Supercomputing | Ausgabe 3/2014
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Abstract
vLock
). The key idea is to map the huge logical lock space to a small fixed physical lock space that can reside in cache during runtime. The virtualization mechanism effectively reduces lock incurred extra memory cost and cache misses with only a slight increase of lock conflict rate, while it preserves high portability for legacy codes by providing Pthreads-like application programming interface. Our further analysis reveals that given the random access pattern, the lock conflict rate is no longer related to the size of vertex set but only the numbers of both physical locks and parallel threads, thus vLock
is independent from graph topologies. This paper presents a complete description of the vLock
method as well as its theoretic foundation. We implemented an vLock
library and evaluated its performance in four classic graph traversal algorithms (BFS, SSSP, CC, PageRank). Experiments on the Intel Xeon E5 eight-core processor show that, compared to Pthreads fine-grained locks, vLock
significantly reduces lock’s cache misses and achieves 4–20 % performance improvement.