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Journal of Electronic Testing
Erschienen in: Journal of Electronic Testing 1/2011

01.02.2011

Fault Diagnosis in Lab-on-Chip Using Digital Microfluidic Logic Gates

verfasst von: Yang Zhao, Krishnendu Chakrabarty

Erschienen in: Journal of Electronic Testing | Ausgabe 1/2011

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Abstract

Fault diagnosis is needed for a lab-on-chip to facilitate defect tolerance using reconfiguration. Previously proposed techniques for reading test outcomes and for pulse-sequence analysis are cumbersome and error-prone. We present a fault-diagnosis method to locate a single defective cell and multiple rows/columns with defective cells in a digital microfluidic array. The proposed method can also locate an unknown number of rows/columns-under-test with defective cells. It utilizes digital microfluidic exclusive-or gates to implement an output compactor. The microfluidic compactor can compress 2 r distinct test outcomes to a r-droplet signature. This approach obviates the need for capacitive sensing test-outcome circuits for analysis. We analyze the probability of misdiagnosis and use the compression ratio as a measure to evaluate the proposed fault-diagnosis method.
Vorheriger Artikel Test Strategies for Electrode Degradation in Bio-Fluidic Microsystems
Nächster Artikel A Design of Linearity Built-in Self-Test for Current-Steering DAC

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Metadaten
Titel
Fault Diagnosis in Lab-on-Chip Using Digital Microfluidic Logic Gates
verfasst von
Yang Zhao
Krishnendu Chakrabarty
Publikationsdatum
01.02.2011
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 1/2011
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-010-5190-7

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