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Erschienen in:
Security and Trust Verification of IoT SoCs Kapitel lesen Erstes Kapitel lesen

2019 | OriginalPaper | Buchkapitel

Fault-Tolerant Implementations of Physically Unclonable Functions on FPGA

verfasst von : Durga Prasad Sahoo, Arnab Bag, Sikhar Patranabis, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty

Erschienen in: Security and Fault Tolerance in Internet of Things

Verlag: Springer International Publishing

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Abstract

Most of the faults in circuits or systems occur due to the unintentional but natural phenomenon (e.g. imperfection in manufacturing process or significant change in the working environment), and thus, these faults are often follow a pattern and comparatively easier detect than the intentional faults. In the context of secure design/system, the adversary (intentionally) injects some faults in the system to bypass the security protection or reveal secret information. Since the adversaries’ fault injection objectives are often very subjective, it is difficult to find a pattern among the faults in a system, and this makes the fault detection and fault recovery difficult in a secure system. In this chapter, we discuss possible intentional faults in an emerging hardware security primitive, known as Physically Unclonable Functions (PUFs). We show how the faults vary over the PUF designs and its applications. In addition, we explain different fault detection circuits and fault recovery techniques which are specific to PUF designs and their implementations on FPGA platforms.

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Vorheriges Kapitel An Approach to Integrating Security and Fault Tolerance Mechanisms into the Military IoT
Nächstes Kapitel Fault Tolerance in 3D-ICs
Literatur
1.
2.
3.
4.
5.
6.
7.
Becker, G.T.: The gap between promise and reality: on the insecurity of XOR Arbiter PUFs. In: Proceedings of 17th International Workshop on Cryptographic Hardware and Embedded Systems (CHES) (2015)
8.
9.
Chen, Q., Csaba, G., Lugli, P., Schlichtmann, U., ührmair, U.R.: The bistable ring PUF: a new architecture for strong physical unclonable functions. In: Proceedings of IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 134 –141 (2011)
10.
Cherif, Z., Danger, J.L., Guilley, S., Bossuet, L.: An easy-to-design PUF based on a single oscillator: the loop PUF. In: Proceedings of 15th Euromicro Conference on Digital System Design (DSD), pp. 156–162 (2012)
11.
Delvaux, J., Verbauwhede, I.: Fault injection modeling attacks on 65 nm Arbiter and RO Sum PUFs via environmental changes. IACR Cryptol. ePrint Archive 2013, 619 (2013)
12.
Delvaux, J., Verbauwhede, I.: Side channel modeling attacks on 65 nm Arbiter PUFs exploiting CMOS device noise. In: IEEE 6th International Symposium on Hardware-Oriented Security and Trust (2013)
13.
Ganji, F., Krämer, J., Seifert, J., Tajik, S.: Lattice basis reduction attack against physically unclonable functions. In: Proceedings of the 22nd ACM SIGSAC Conference on Computer and Communications Security (CCS), pp. 1070–1080 (2015)
14.
Holcomb, D.E., Burleson, W.P., Fu, K.: Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans. Comput. 58(9), 1198–1210 (2009)MathSciNetCrossRef
15.
Karaklajic, D., Schmidt, J., Verbauwhede, I.: Hardware designer’s guide to fault attacks. IEEE Trans. VLSI Syst. 21(12), 2295–2306 (2013)CrossRef
16.
Koçabas, Ü., Peter, A., Katzenbeisser, S., Sadeghi, A.: Converse PUF-based authentication. In: Trust and Trustworthy Computing—5th International Conference, TRUST 2012, Vienna, Austria, 13–15 June 2012. Proceedings, pp. 142–158 (2012)
17.
18.
Lim, D.: Extracting Secret Keys from Integrated Circuits. Master’s thesis, MIT, USA (2004)
19.
Maes, R.: Physically Unclonable Functions—Constructions, Properties and Applications. Springer (2013)
20.
Maes, R., van der Leest, V., van der Sluis, E., Willems, F.: Secure key generation from biased PUFs. In: Proceedings of 17th International Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp. 517–534 (2015)
21.
Maiti, A., Nagesh, R., Reddy, A., Schaumont, P.: Physical unclonable function and true random number generator: a compact and scalable implementation. In: Proceedings of ACM Great Lakes Symposium on VLSI, pp. 425–428 (2009)
22.
Maiti, A., Gunreddy, V., Schaumont, P.: A systematic method to evaluate and compare the performance of physical unclonable functions. IACR Cryptol. ePrint Archive 2011, 657 (2011)
23.
Majzoobi, M., Koushanfar, F., Devadas, S.: FPGA PUF using programmable delay lines. In: IEEE International Workshop on Information Forensics and Security (WIFS), pp. 1–6 (2010)
24.
Majzoobi, M., Rostami, M., Koushanfar, F., Wallach, D.S., Devadas, S.: Slender PUF protocol: a lightweight, robust, and secure authentication by substring matching. In: Proceedings of IEEE Symposium on Security and Privacy Workshops, pp. 33–44 (2012)
25.
Malkin, T., Standaert, F., Yung, M.: A comparative cost/security analysis of fault attack countermeasures. In: Proceedings of Fault Diagnosis and Tolerance in Cryptography (FDTC), pp. 159–172 (2006)
26.
Merli, D., Schuster, D., Stumpf, F., Sigl, G.: Semi-invasive EM attack on FPGA RO PUFs and countermeasures. In: Proceedings of the 6th Workshop on Embedded Systems Security (WESS 2011) (2011)
27.
Rührmair, U., Sehnke, F., Sölter, J., Dror, G., Devadas, S., Schmidhuber, J.: Modeling attacks on physical unclonable functions. In: Proceedings of 17th ACM Conference on Computer and Communications Security (CCS), pp. 237–249. ACM, New York, NY, USA (2010)
28.
Rührmair, U., Sölter, J., Sehnke, F., Xu, X., Mahmoud, A., Stoyanova, V., Dror, G., Schmidhuber, J., Burleson, W., Devadas, S.: PUF modeling attacks on simulated and silicon data. IEEE Trans. Inf. Forensics Secur. 8(11), 1876–1891 (2013)CrossRef
29.
Rührmair, U., Xu, X., Sölter, J., Mahmoud, A., Majzoobi, M., Koushanfar, F., Burleson, W.P.: Efficient power and timing side channels for physical unclonable functions. In: Proceedings of 16th International Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp. 476–492 (2014)CrossRef
30.
Sahoo, D.P.: Design and Analysis of Secure Physically Unclonable Function Compositions. Ph.D. thesis (2017)
31.
Sahoo, D.P., Saha, S., Mukhopadhyay, D., Chakraborty, R.S., Kapoor, H.: Composite PUF: a new design paradigm for physically unclonable functions on FPGA. In: Proceedings of IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 50–55 (2014)
32.
33.
Suh, G.E., Devadas, S.: Physical unclonable functions for device authentication and secret key generation. In: Proceedings of Design Automation Conference (DAC), pp. 9–14. ACM Press, New York, NY, USA (2007)
34.
Tajik, S., Dietz, E., Frohmann, S., Seifert, J., Nedospasov, D., Helfmeier, C., Boit, C., Dittrich, H.: Physical characterization of Arbiter PUFs. In: Proceedings of 16th International Workshop Cryptographic Hardware and Embedded Systems (CHES), pp. 493–509 (2014)CrossRef
35.
Tajik, S., Lohrke, H., Ganji, F., Seifert, J.P., Boit, C.: Laser fault attack on physically unclonable functions. In: Proceedings of 12th Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC) (2015)
36.
Tobisch, J., Becker, G.T.: On the scaling of machine learning attacks on PUFs with application to noise bifurcation. In: Proceedings of 11th International Workshop on Radio Frequency Identification: Security and Privacy Issues (RFIDsec), pp. 17–31 (2015)CrossRef
Metadaten
Titel
Fault-Tolerant Implementations of Physically Unclonable Functions on FPGA
verfasst von
Durga Prasad Sahoo
Arnab Bag
Sikhar Patranabis
Debdeep Mukhopadhyay
Rajat Subhra Chakraborty
Copyright-Jahr
2019
Buch
Security and Fault Tolerance in Internet of Things

Print ISBN: 978-3-030-02806-0

Electronic ISBN: 978-3-030-02807-7

Copyright-Jahr: 2019

DOI
https://doi.org/10.1007/978-3-030-02807-7_7

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