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Fine-time resolution measurements are attracting increasing attention in the high-energy-physics (HEP) community, where a large number of measurement channels must often be realized with a single ASIC. In this contribution, a multi-channel time-to-digital converter (TDC) architecture with a delay-locked-loop (DLL) in its first stage and a resistive interpolation scheme in its second stage is presented. The size of the TDC’s least-significant-bit (LSB) is controlled by a reference clock and so can be continuously adjusted from 5 to 20 ps. A global calibration scheme that avoids the need to calibrate each channel separately is also used. Critical design aspects like device mismatch, supply noise sensitivity and process-voltage and temperature (PVT) variation are discussed. When realized in a 130 nm technology, the prototype ASIC achieved a single-shot resolution of better than 2.5 ps-rms. The measured integral-non-linearity (INL) and differential-non-linearity (DNL) were found to be ±1.4 LSB and ±0.9 LSB respectively.
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S. White, M. Chiu, M. Diwan, G. Atoyan, and V. Issakov, “Design of a 10 picosecond Time of Flight Detector using Avalanche Photodiodes,” 2009.
R. Forty, and M. Charles, “Torch: a novel time-of-flight detector concept,” CERN, Geneva, Tech. Rep. LHCb-PUB-2009-030. CERN-LHCb-PUB-2009-030, Nov 2009.
L. Adamczyk, “AFP: A proposal to install proton detectors at 220 m around ATLAS to complement the ATLAS high luminosity physics program,” 2011. [Online]. Available: http://atlas-project-lumi-fphys.web.cern.ch/atlas-project-lumi-fphys/default.html
N. Harnew, “TORCH: A large-area detector for precision time-of-flight measurements at LHCb,” Physics Procedia, vol. 37, no. 0, pp. 626 – 633, 2012, Proceedings of the 2nd International Conference on Technology and Instrumentation in Particle Physics (TIPP 2011). [Online]. Available: http://www.sciencedirect.com/science/article/pii/S1875389212017427
M. Lee, and A. Abidi, “A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue, ” IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 769 –777, April 2008.
P. Keranen, K. Maatta, and J. Kostamovaara, “Wide-range time-to-digital converter with 1-ps single-shot precision,” IEEE Transactions on Instrumentation and Measurement, vol. 60, no. 9, pp. 3162 –3172, Sept 2011.
S. Mandai, and E. Charbon, “A 128-channel, 8.9-ps LSB, column-parallel two-stage TDC based on time difference amplification for time-resolved imaging,” IEEE Transactions on Nuclear Science, vol. 59, no. 5, pp. 2463–2470, 2012.
D. Schwartz, E. Charbon, and K. Shepard, “A single-photon avalanche diode array for fluorescence lifetime imaging microscopy, “ IEEE Journal of Solid-State Circuits, vol. 43, no. 11, pp. 2546 –2557, Nov 2008.
K. Kundert, “Modeling jitter in PLL-based frequency synthesizers,” 2003.
L. Perktold and J. Christiansen, “A high time-resolution (<3 ps-rms) time-to-digital converter for highly integrated designs,” in Instrumentation and Measurement Technology Conference (I2MTC), 2013 IEEE International, 2013.
L. Perktold and J. Christiansen, “A flexible 5 ps bin-width timing core for next generation high-energy-physics time-to-digital converter applications,” in 2012 8th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2012, pp. 1–4.
J. Maneatis, “Low-jitter and process independent DLL and PLL based on self biased techniques,” in 1996 IEEE International Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., Feb 1996, pp. 130–131, 430.
S. Anand and B. Razavi, “A CMOS clock recovery circuit for 2.5-Gb/s NRZ data,” IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 432 –439, Mar 2001.
S. Henzler, S. Koeppe, D. Lorenz, W. Kamp, R. Kuenemund, and D. Schmitt-Landsiedel, “A local passive time interpolation concept for variation-tolerant high-resolution time-to-digital conversion,” IEEE Journal of Solid-State Circuits, vol. 43, no. 7, pp. 1666 –1676, July 2008.
M.-W. Chen, D. Su, and S. Mehta, “A calibration-free 800 MHZ fractional-n digital PLL with embedded TDC,” IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp. 2819–2827, Dec 2010.
E. Martin et al., “The 5 ns peaking time transimpedance front end amplifier for the silicon pixel detector in the NA62 Gigatracker,” in Nuclear Science Symposium Conference Record (NSS/MIC), 2009 IEEE, 2009, pp. 381–388.
J. Christiansen, “Manual: HPTDC—high performance time to digital converter,” 2004. [Online]. Available: http://tdc.web.cern.ch/tdc/hptdc/docs/hptdc_manual_ver2.2.pdf
E. Bayer, P. Zipf, and M. Traxler, “a multichannel high-resolution (5 ps RMS between two channels) time-to-digital converter (TDC) implemented in a field programmable gate array (FPGA)”, in Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2011 IEEE, 2011, pp. 876–879.
J.-P. Jansson, A. Mantyniemi, and J. Kostamovaara, “A CMOS time-to-digital converter with better than 10 ps single-shot precision,” IEEE Journal of Solid-State Circuits, vol. 41, no. 6, pp. 1286–1296, 2006.
- Fine-Time Resolution Measurements for High Energy Physics Experiments