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Erschienen in:
2017 | OriginalPaper | Buchkapitel
9. Finite-State Machines
verfasst von : Vaibbhav Taraate
Erschienen in: PLD Based Design with VHDL
Verlag: Springer Singapore
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Abstract
This chapter describes the efficient FSM coding using VHDL constructs. The FSMs are of two types: Moore and Mealy, and this chapter focuses on the RTL design for the Moore and Mealy machines. Even this chapter discusses about the different encoding methods for FSM, and the FSM examples are described using binary, gray, and one-hot encoding method. The examples such as sequence detector and parity checker are useful in the real practical world and are discussed in this chapter. Even this chapter is useful to understand the importance of the multiple process FSM. The key design guidelines for FSM are described with the performance improvement techniques.