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Semiconductor devices reached the nanoscale in the 2000s and have continued to shrink their features in accordance with Moore’s law. Semiconductor packaging, which is critical to ensure connectivity of these fine-featured semiconductor devices, has also kept pace with Moore’s law scaling to enable products to take advantage of the performance scaling opportunities afforded by silicon scaling. In doing so, packaging has been increasingly challenged to provide requisite interconnect scaling, form-factor scaling, process scaling, enhanced thermal management, improved signal integrity, improved power delivery, and adequate thermomechanical reliability in increasingly diverse applications. This chapter systematically examines the evolution, challenges, and opportunities of different aspects of flip-chip package scaling, typically used for high-performance silicon. Materials continue to play a critical role in the evolution of flip-chip packaging, and their influence and impact are also discussed to highlight their contributions and importance.
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Although there is a considerable amount of active research in non-solder-based area array interconnects, solder-based flip-chip interconnects are currently the most widely used die-to-die and die-to-package interconnects, for a variety of reasons including ease of manufacturing, interconnect compliance that reduces stress on the silicon backend layers, etc. In this chapter focus is restricted to packaging of nanoscale devices using solder-based flip-chip interconnects.
Focus on this chapter will be restricted to area array interconnects and will not cover wire-bonded interconnects in 3D die stacks.
Although the source is somewhat dated, it is the last time a formal pitch scaling target was published. As of 2017, the lowest pitch in commercially available stacked memories is 40 μm [ 11].
Thermal compression bonding (TCB) is the most common method of chip attach for fine-pitch die-die interconnects [ 13].
These processes are also referred to as No-Flow processes. The underfill and flux materials as integrated together and the underfill and chip attach processes are integrated as well [ 17].
Underfill CTE is modulated by filler content and tailored to minimize thermomechanical stresses.
The cored package technology is described here as a superset of substrate technologies. In recent years, there has been considerable focus on developing thin coreless package substrate technologies that essentially consist only of the dielectric layers [ 24] and wafer-level fan-out technologies that use wafer-level patterning processes to enable interconnect scaling [ 25].
Large packages used in high-performance products use pitches in the 1.00 mm range to pitches in the 0.8 mm range, while smaller packages used in handheld devices have seen pitches as low as 0.4 mm.
Management of thermal transients is also an important consideration during testing of semiconductor devices and when they are expected to operate in burst modes; however this is beyond the scope of this chapter.
In addition to particle-filled polymers listed, solders are also used as TIM materials. Solders have significantly higher bulk thermal conductivity (30–50 W/(m-°K)) compared to filled polymers (~3 W/(m-°K)); however they require very different and potentially expensive processing conditions.
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- Flip-Chip Packaging for Nanoscale Silicon Logic Devices: Challenges and Opportunities
- Chapter 31
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