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The design, materials, process, fabrication, and reliability of fan-out wafer-level packaging (FOWLP) with chip-first and die face-up method are presented in this chapter. Emphasis is placed on the issues and their solutions (such as reconstituted carrier, die-attach film placement, pitch compensation, die shift, epoxy molding compound dispensing, compression molding, warpage, and Cu revealing) during the fabrication of a very large test chip (10 mm × 10 mm × 150 µm) and test package (13.47 mm × 13.47 mm), and three redistribution layers (RDLs) with the smallest line width/spacing = 5 µm/5 µm. The FOWLP test package on a six-layer printed circuit board (PCB) is subjected to thermal cycling and drop tests. Recommendations of process integration and guidelines on FOWLP with chip-first and die face-up are provided.
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- FOWLP: Chip-First and Die Face-Up
John H. Lau
- Springer Singapore
- Chapter 6