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2018 | OriginalPaper | Buchkapitel

7. FOWLP: Chip-Last or RDL-First

verfasst von : John H. Lau

Erschienen in: Fan-Out Wafer-Level Packaging

Verlag: Springer Singapore

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Abstract

Since 2006, NEC Electronics Corporation (now Renesas Electronics Corporation) has been developing a novel SMAFTI (SMArt chip connection with feedthrough interposer) packaging technology for inter-chip wideband data transfer, 3D stacked memory integrated on logic devices, system in wafer-level package (SiWLP), and “RDL-first” fan-out wafer-level packaging. In this chapter, three RDL (redistribution layer) fabrication methods for chip-last FOWLP (fan-out wafer-level packaging) are briefly mentioned.

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Literatur
1.
Zurück zum Zitat Kurita, Y., K. Soejima, K. Kikuchi, M. Takahashi, M. Tago, M. Koike, et al. 2006. A Novel “SMAFTI” Package for Inter-Chip Wide-Band Data Transfer. In IEEE/ECTC Proceedings, 2006, 289–297. Kurita, Y., K. Soejima, K. Kikuchi, M. Takahashi, M. Tago, M. Koike, et al. 2006. A Novel “SMAFTI” Package for Inter-Chip Wide-Band Data Transfer. In IEEE/ECTC Proceedings, 2006, 289–297.
2.
Zurück zum Zitat Kawano, M., S. Uchiyama, Y. Egawa, N. Takahashi, Y. Kurita, K. Soejima, et al. 2006. A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer. In IEEE/IEMT Proceedings, 2006, 581–584. Kawano, M., S. Uchiyama, Y. Egawa, N. Takahashi, Y. Kurita, K. Soejima, et al. 2006. A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer. In IEEE/IEMT Proceedings, 2006, 581–584.
3.
Zurück zum Zitat Kurita, Y., S. Matsui, N. Takahashi, K. Soejima, M. Komuro, M. Itou, et al. 2007. A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology. In IEEE/ECTC Proceedings, 2007, 821–829. Kurita, Y., S. Matsui, N. Takahashi, K. Soejima, M. Komuro, M. Itou, et al. 2007. A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology. In IEEE/ECTC Proceedings, 2007, 821–829.
4.
Zurück zum Zitat Kawano, M., N. Takahashi, Y. Kurita, K. Soejima, M. Komuro, and S. Matsui. 2008. A 3-D Packaging Technology for Stacked DRAM with 3 Gb/s Data Transfer. IEEE Transactions on Electron Devices 55 (7): 1614–1620. Kawano, M., N. Takahashi, Y. Kurita, K. Soejima, M. Komuro, and S. Matsui. 2008. A 3-D Packaging Technology for Stacked DRAM with 3 Gb/s Data Transfer. IEEE Transactions on Electron Devices 55 (7): 1614–1620.
5.
Zurück zum Zitat Motohashi, N., Y. Kurita, K. Soejima, Y. Tsuchiya, and M. Kawano. 2009. SMAFTI Package with Planarized Multilayer Interconnects. In IEEE/ECTC Proceedings, 2009, 599–606. Motohashi, N., Y. Kurita, K. Soejima, Y. Tsuchiya, and M. Kawano. 2009. SMAFTI Package with Planarized Multilayer Interconnects. In IEEE/ECTC Proceedings, 2009, 599–606.
6.
Zurück zum Zitat Kurita, M., S. Matsui, N. Takahashi, K. Soejima, M. Komuro, M. Itou, et al. 2009. Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology. IEEE Transactions on Advanced Packaging, 2009, 657–665. Kurita, M., S. Matsui, N. Takahashi, K. Soejima, M. Komuro, M. Itou, et al. 2009. Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology. IEEE Transactions on Advanced Packaging, 2009, 657–665.
7.
Zurück zum Zitat Kurita, Y., N. Motohashi, S. Matsui, K. Soejima, S. Amakawa, K. Masu, et al. 2009. SMAFTI Packaging Technology for New Interconnect Hierarchy. In Proceedings of IITC, 2009, 220–222. Kurita, Y., N. Motohashi, S. Matsui, K. Soejima, S. Amakawa, K. Masu, et al. 2009. SMAFTI Packaging Technology for New Interconnect Hierarchy. In Proceedings of IITC, 2009, 220–222.
8.
Zurück zum Zitat Kurita, Y., T. Kimura, K. Shibuya, H. Kobayashi, F. Kawashiro, N. Motohashi, et al. 2010. Fan-Out Wafer Level Packaging with Highly Flexible Design Capabilities. In IEEE/ECTC Proceedings, 2010, 1–6. Kurita, Y., T. Kimura, K. Shibuya, H. Kobayashi, F. Kawashiro, N. Motohashi, et al. 2010. Fan-Out Wafer Level Packaging with Highly Flexible Design Capabilities. In IEEE/ECTC Proceedings, 2010, 1–6.
9.
Zurück zum Zitat Motohashi, N., T. Kimura, K. Mineo, Y. Yamada, T. Nishiyama, K. Shibuya, et al. 2011. System in a Wafer Level Package Technology with RDL-First Process. In IEEE/ECTC Proceedings, 2011, 59–64. Motohashi, N., T. Kimura, K. Mineo, Y. Yamada, T. Nishiyama, K. Shibuya, et al. 2011. System in a Wafer Level Package Technology with RDL-First Process. In IEEE/ECTC Proceedings, 2011, 59–64.
10.
Zurück zum Zitat Lau, J.H., N. Fan, and M. Li. 2016. Design, Material, Process, and Equipment of Embedded Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 20: 38–44. Lau, J.H., N. Fan, and M. Li. 2016. Design, Material, Process, and Equipment of Embedded Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 20: 38–44.
11.
Zurück zum Zitat Huemoeller, R., and C. Zwenger. 2015. Silicon Wafer Integrated Fan-Out Technology. Chip Scale Review 34–37. Huemoeller, R., and C. Zwenger. 2015. Silicon Wafer Integrated Fan-Out Technology. Chip Scale Review 34–37.
12.
Zurück zum Zitat Che, F.X., D. Ho, M. Ding, and D. MinWoo. 2016. Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging. In IEEE/ECTC Proceedings, 2016, 1879–1885. Che, F.X., D. Ho, M. Ding, and D. MinWoo. 2016. Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging. In IEEE/ECTC Proceedings, 2016, 1879–1885.
13.
Zurück zum Zitat Rao, V., C. Chong, D. Ho, D. Zhi, C. Choong, S. Lim, D. Ismael, and Y. Liang. 2016. Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications. In IEEE/ECTC Proceedings, 2016, 1522–1529. Rao, V., C. Chong, D. Ho, D. Zhi, C. Choong, S. Lim, D. Ismael, and Y. Liang. 2016. Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications. In IEEE/ECTC Proceedings, 2016, 1522–1529.
14.
Zurück zum Zitat Ma, M., S. Chen, P.I. Wu, A. Huang, C.H. Lu, A. Chen, C. Liu, and S. Peng. 2016. The Development and the Integration of the 5 μm to 1 μm Half Pitches Wafer Level Cu Redistribution Layers. In IEEE/ECTC Proceedings, 2016, 1509–1614. Ma, M., S. Chen, P.I. Wu, A. Huang, C.H. Lu, A. Chen, C. Liu, and S. Peng. 2016. The Development and the Integration of the 5 μm to 1 μm Half Pitches Wafer Level Cu Redistribution Layers. In IEEE/ECTC Proceedings, 2016, 1509–1614.
15.
Zurück zum Zitat Kim, Y., J. Bae, M. Chang, A. Jo, J. Kim, S. Park, D. Hiner, M. Kelly, and W. Do. 2017. SLIM™, High Density Wafer Level Fan-out Package Development with Submicron RDL. In IEEE/ECTC Proceedings, 2017, 18–13. Kim, Y., J. Bae, M. Chang, A. Jo, J. Kim, S. Park, D. Hiner, M. Kelly, and W. Do. 2017. SLIM™, High Density Wafer Level Fan-out Package Development with Submicron RDL. In IEEE/ECTC Proceedings, 2017, 18–13.
16.
Zurück zum Zitat Hiner, D., M. Kolbehdari, M. Kelly, Y. Kim, W. Do, J. Bae, M. Chang, and A. Jo. 2017. SLIM™ Advanced Fan-out Packaging for High Performance Multi-die Solutions. In IEEE/ECTC Proceedings, 2017, 575–580. Hiner, D., M. Kolbehdari, M. Kelly, Y. Kim, W. Do, J. Bae, M. Chang, and A. Jo. 2017. SLIM™ Advanced Fan-out Packaging for High Performance Multi-die Solutions. In IEEE/ECTC Proceedings, 2017, 575–580.
17.
Zurück zum Zitat Lau, J.H. 2016. Recent Advances and New Trends in Flip Chip Technology. ASME Transactions, Journal of Electronic Packaging 138 (3): 1–23. Lau, J.H. 2016. Recent Advances and New Trends in Flip Chip Technology. ASME Transactions, Journal of Electronic Packaging 138 (3): 1–23.
18.
Zurück zum Zitat Lau, J.H., P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, K. Saito, Y. Hsin, P. Chang, Y. Chang, J. Chen, S. Chen, C. Wu, H. Chang, C. Chien, C. Lin, T. Ku, R. Lo, and M. Kao. 2013. Redistribution Layers (RDLs) for 2.5D/3D IC Integration. In Proceedings of IMAPS International Symposium on Microelectronics, October 2013, 434–441. Lau, J.H., P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, K. Saito, Y. Hsin, P. Chang, Y. Chang, J. Chen, S. Chen, C. Wu, H. Chang, C. Chien, C. Lin, T. Ku, R. Lo, and M. Kao. 2013. Redistribution Layers (RDLs) for 2.5D/3D IC Integration. In Proceedings of IMAPS International Symposium on Microelectronics, October 2013, 434–441.
19.
Zurück zum Zitat Lau, J.H., P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, K. Saito, Y. Hsin, P. Chang, Y. Chang, J. Chen, S. Chen, C. Wu, H. Chang, C. Chien, C. Lin, T. Ku, R. Lo, and M. Kao. 2014. Redistribution Layers (RDLs) for 2.5D/3D IC Integration. IMAPS Transactions, Journal of Microelectronic Packaging 11 (1): 16–24.CrossRef Lau, J.H., P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, K. Saito, Y. Hsin, P. Chang, Y. Chang, J. Chen, S. Chen, C. Wu, H. Chang, C. Chien, C. Lin, T. Ku, R. Lo, and M. Kao. 2014. Redistribution Layers (RDLs) for 2.5D/3D IC Integration. IMAPS Transactions, Journal of Microelectronic Packaging 11 (1): 16–24.CrossRef
Metadaten
Titel
FOWLP: Chip-Last or RDL-First
verfasst von
John H. Lau
Copyright-Jahr
2018
Verlag
Springer Singapore
DOI
https://doi.org/10.1007/978-981-10-8884-1_7

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