In this paper an efficient approach is presented to design and implement a high speed RRC pulse shaping filter for digital up converter (DUC) section of
adios (SDR). The implementation is based on efficient utilization of embedded DSP48E slices of the target device to enhance the speed of complex multipliers used in implementation of pulse shaping filters. It is an efficient method because the use of DSP48E slices not only increases the speed but also saves the general purpose resources on the target device. The root raised cosine (RRC) filter is designed and simulated in direct and transposed form with Matlab and Xilinx AccelDSP, synthesized with Xilinx Synthesis Tool (XST), and implemented on Virtex-5 based XC5VSX50T FPGA device. The proposed transposed structure can operate at an estimated frequency of 146.5 MHz as compared to 69.1 MHz in case of direct form structure by consuming almost same embedded DSP48E slices to provide cost effective solution for mobile and wireless communication systems.