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Journal of Computational Electronics
Erschienen in: Journal of Computational Electronics 4/2018

22.08.2018

Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET

verfasst von: Dip Joti Paul, Md. Abdullah-Al-Kaiser, Md. Shofiqul Islam, Quazi D. M. Khosru

Erschienen in: Journal of Computational Electronics | Ausgabe 4/2018

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Abstract

An analytical model was developed to calculate the potential distribution for a gate-underlap double-gate tunnel FET. The electrostatic potential of the device was derived using the two-dimensional Poisson’s equation, incorporating the fringing electric field in the gate-underlap surface and employing a conformal mapping method. In addition to analytical potential modeling, the electric field and drain current were evaluated to investigate the device performance. Excellent agreement with technology computer-aided design (TCAD) simulation results was observed. The dependence of the ambipolar current on the spacer oxide dielectric constant, spacer length, channel length, and gate material thickness was examined using the proposed model. The effects of the variation of all of these parameters were well predicted, and the model reveals that use of a low-\(\kappa \) spacer dielectric combined with a high-\(\kappa \) gate dielectric results in the minimal ambipolar current for the device.
Vorheriger Artikel A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs
Nächster Artikel Updated structure of vertical double-diffused MOSFETs for irradiation hardening against single events

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Metadaten
Titel
Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET
verfasst von
Dip Joti Paul
Md. Abdullah-Al-Kaiser
Md. Shofiqul Islam
Quazi D. M. Khosru
Publikationsdatum
22.08.2018
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 4/2018
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-018-1234-5

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