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Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield.
Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing.
From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems.
Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing.

Inhaltsverzeichnis

Frontmatter

1. Introduction

Abstract
Over the years, there has been a large increase in functionality available on a single integrated circuit. From 2,300 transistors on a chip in 1971 [1], the state-of-the art designs of today have progressed to about 5 million transistors [2], [3]. The number of transistors on a single die has approximately doubled every two years, as predicted by Moore’s law [4].
Jitendra B. Khare, Wojciech Maly

2. Background

Abstract
In this chapter, we briefly discuss previous attempts at modeling contamination in IC manufacturing and its effect on yield modeling. The relevance of these models in modern manufacturing environments is also discussed.
Jitendra B. Khare, Wojciech Maly

3. Contamination-Defect-Fault (CDF) Simulation

Abstract
As indicated in Chapter 2, the main shortcoming of the disk model was its inability to model faults starting from the actual failure mechanism, rather than from the spot defect level. It was also observed in the model validation experiment [1], [2], [3] and in the experiment described in [4] that most failures in ICs were caused by contamination which deposited on the IC during some processing step. To increase the fidelity of modeling, therefore, it is essential to begin all fault and yield model studies/simulations at the contamination level.
Jitendra B. Khare, Wojciech Maly

4. CDF Mapper Codef

Abstract
In conjunction with the new contamination model and in accordance with the simulation requirements (both described in Chapter 3), a contamination-defect-fault mapping tool CODEF (Contamination-Defect-Fault) [1], [2], [3] has been developed. A block diagram of the simulator is shown in Figure 1. CODEF accepts as inputs (a) layout description of the IC cell under analysis in CIF format [4], (b) description of the fabrication process (process recipe) in the PREDITOR format [5], [6], and (c) statistics of contamination parameters for each processing step of interest.
Jitendra B. Khare, Wojciech Maly

5. CODEF - Applications

Abstract
This chapter discusses potential applications of CODEF for IC manufacturing. Three main areas are investigated in detail: (a) yield estimation, (b) fault modeling, and (c) failure analysis.
Jitendra B. Khare, Wojciech Maly

6. Possible Extensions

Abstract
The new contamination model in conjunction with CODEF can be successfully used to solve a number of IC manufacturing problems related to fault modeling and failure analysis. In order to make CODEF more universal and efficient, though, work must be done in a number of areas. These are outlined below.
Jitendra B. Khare, Wojciech Maly

7. Conclusion

Abstract
As the cost of manufacturing increases sharply, there is emphasis on reducing costs by improving the efficiency and accuracy of manufacturing tasks such as fault modeling, failure analysis and yield estimation. As a result, more attention is being given to understanding the relationship between contamination depositing on the wafer during IC fabrication, and the resulting functional failure.
Jitendra B. Khare, Wojciech Maly

Backmatter

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