On the brink of introducing the fifth generation (5G) of cellular networks, the art of radio-frequency (RF) integrated circuit design has never seen such a wide spread of diverging requirements:
On the one hand, ubiquitous sensor networks are mandating power budgets in the order of micro-watt. They should be constructed as energy-autonomous, wireless, low-cost sensor nodes. This demand is caused by massive deployment scenarios of billions of devices, which makes wires and batteries unpractical. As a result, the desire for the radio nodes to harvest their operational energy from the environment emerges.
On the other hand, the recent and ongoing realization of gigabit-per-second capable cellular modems is driving hardware and power requirements to extremes. To overcome hardware limitations, introduced by analog impairments, digital correction and alignment algorithms are employed for compensation. These factors call for usage of expensive advanced CMOS technology nodes and increased utilization of digital signal processing techniques.
In this paper, we recap ongoing trends and developments for ultra-low power and high-end transceiver (TRX) designs using CMOS technology nodes ranging from low-cost to highest performance.
1 Introduction
Taking a look at the recent forecast on mobile communication from the Ericsson mobility report [10] the number of mobile phone subscriptions should experience a small growth rate of approximately 3% per year, compared to an annual growth of roughly 20% for internet-of-things (IoT) devices, as visualized in Fig. 1(a). Simultaneously the total traffic for mobile phones, shown in Fig. 1(b), is expected to increase by a yearly rate of more than 40%. This illustrates the tendency towards highest performance data services in 5G networks with Gbps range data rates to increase average speed per user as well as network capacity. To achieve such performance data, novel circuit design strategies are needed and hardware limitations need to be compensated by digital correction and alignment algorithms. Often the most expensive and advanced CMOS technology nodes, i.e. 14 nm FinFET [17], are used, since they imply best performance and highest integration level for the integrated circuits while still maintaining decently low power consumption. Figure 2 shows a perspective on the costs of development and verification for intellectual properties (IPs) in different technologies as outlined in [16]. With a large production volume for the potential application, the enormous development and fabrication costs of those extraordinary small technology nodes can be justified. Furthermore, these technologies allow for advanced high speed digital signal processing (DSP) techniques. Section 3 will recap ongoing developments and impairments in high performance mobile transceivers.
Perspective on IP developing and qualification cost in different technology nodes [16]
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With a predicted number of more than fifteen billion short-range IoT-devices in 2022, power supply will be a certain issue. Since powering billions of devices using batteries is impractical for ecological and economical reasons, it is desirable that IoT-devices harvest their operational energy from their environment. Therefore, the associated transceiver design is discussed and must incorporate power efficiency measures in order to get along with the limited amount of energy available from the energy-harvesting techniques.
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At the same time IoT-devices should cover a broad range of applications, including specialized implementations with relatively low quantities to be manufactured, e.g. for specialized medical applications or environmental monitoring, and simultaneously provide lowest product cost. As a reasonable consequence to fulfill these requirements, mature CMOS technology nodes (like 130 nm or 180 nm) are required instead of using the most advanced technologies.
Therefore, in Sect. 2.1, we recap recent publications and common energy-reduction techniques for ultra-low-power (ULP) transceiver design in 180 nm technologies for the frequency band at around 868–915 MHz since the corresponding wavelength offers a good compromise between maximum-range of operation and antenna-size [34]. In Sect. 2.2 various approaches of energy harvesting are summarized and available power budgets discussed.
In Sect. 3 we summarize ongoing trends in 5G wireless communication and present the utilized most advanced CMOS technology nodes and discuss the corresponding circuit design challenges caused by the strong scaling of circuit structures. Finally, Sect. 4 summarizes and concludes the paper.
2 Ultra-low-power transceiver design and energy harvesting
The growing IoT market demands a large amount of self-powered devices with long-term deployment. In order to increase the lifespan of those devices for a given energy source, the power consumption of every single component has to be minimized. A summary of the state-of-the-art can be found in [29]. Especially the wireless data transmission of such an IoT sensor node consumes a lot of power and thus needs to be thoroughly optimized. Furthermore, an approach to extend the lifetime of a device is to harvest energy from the environment – either instead of or in addition to the battery.
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Consequently, the following section proposes methods to design power saving ultra-low-power (ULP) transceivers and afterwards recaps some recent energy harvesting concepts.
2.1 Energy-efficient transceiver architectures
The typical approach to design transceivers for high performance applications is to utilize zero- or low intermediate frequency (IF) IQ-based architectures as shown in Fig. 3(a) [19]. This architecture transmits data by applying spectrally efficient complex modulation and demodulation schemes like Quadrature-Amplitude-Modulation (QAM) or Phase-Shift-Keying (PSK). However, the structure suffers from a high power consumption due to the dual modulation paths and the generation of the local oscillator signals. Thus, in order to save power, it is reasonable to reduce the amount of energy hungry components to a minimum while also reducing the overall systems complexity. For this reason, Frequency-Shift-Keying (FSK) or Amplitude-Shift-Keying (ASK) are used because they typically omit IQ-modulation/demodulation paths by using envelope detection for ASK for example. Figure 3(b) pictures a generic low-complexity transceiver structure.
Fig. 3.
Generic transceiver architectures for time-division-duplexing (TDD): (a) zero-IF architecture, and (b) ultra-low-power architecture
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Depending on the application, ULP transmitters generate the radio frequency (RF) using a phase-locked-loop (PLL) and directly transmit the modulated signal. Such transmitter architectures can be summarized as PLL-based transmitters [15], and are often used in Bluetooth Low Energy (BLE) and Wireless Body Area Network (WBAN) applications [6]. PLL-based transmitters provide low phase noise and good frequency stability at the cost of increased power consumption. Nevertheless, in order to further reduce power, the PLL in the transmitter path can either be replaced by a high-quality (Q) oscillator, directly resonating at RF [9] or IF [26], or can fully be omitted by using a free running oscillator [3, 8] at the cost of reduced frequency- and phase-stability, e.g. caused by temperature, supply voltage, or process variations. Consequently, for this type of transmitter, modulation schemes like On-Off-Keying (OOK) are used since they do not require good frequency accuracy. However, the modulated signals have to fulfill the applicable local authority and spectral regulations which can be challenging.
The proposed generic structure in Fig. 3(b) shows a voltage controlled oscillator (VCO) which is shared among transmitter and receiver. During receive times the signal is injected into the VCO causing the oscillation to lock to a certain frequency and simultaneously modulating the amplitude [27]. This results in an amplification of the received signal dependent on the quality of the LC-tank within the VCO. This concept is used in the so called injection-locked [3] or Q-enhanced [8] receivers. In order to improve sensitivity, the generic structure is easily modified to make use of the super-regenerative concept, originally proposed by Armstrong [2]. If the desired communication range is short, the receiver can further be simplified by omitting the injection-step and directly demodulate the envelope as demonstrated in [18].
In addition to the energy-efficient architectures for each building block of the overall system, the overall power consumption can further be reduced by implementing duty-cycling or wake-up structures. During duty-cycling, the transceiver operation is separated in active and inactive states, defined by the duty-cycling ratio. This method allows to trade in the maximum achievable data rate for reduced power consumption [5]. Typically, wake-up structures are implemented using always-on diode-detector based receivers in order to detect a specified low-rate wake-up sequence. Correlation methods can be used to improve the sensitivity of the additional wake-up receiver [24].
2.2 Energy harvesting
There are two popular possibilities to harvest energy from the environment, using either incidental electromagnetic (EM) waves in the MHz- up to GHz-range or ambient light.1 A general drawback is that the available spectral power density is quite low. For example, the transmitter of the potential energy source could be located several kilometers away from the energy harvesting system itself. Because of the strong decay of the EM far-field, the RF output power of the transmitter should often be in the kilo-watts region, which is usually best fulfilled by digital TV broadcast stations. As experimentally demonstrated in downtown Tokyo, a micro-controller was powered wirelessly by 9 TV channels in the frequency range of 512–566 MHz of a local TV broadcast station 6.3 km away [32]. The measured average harvested DC-power of the system was ≈15–17 μW at 4.1 V, whereby the system consisted of a relatively large log-periodic antenna, a discrete RF charge-pump, and the PIC24F micro-controller. Currently, similar experiments are carried out for energy harvesting from LTE mobile communication links [25].
Besides harvesting generally available ambient RF-energy, it is also possible to use a local RF-power-transmitter to energize several surrounding mobile nodes in a range of a few meters. For example, the frequency band at the UHF ISM band 902–928 MHz can be utilized where the propagation losses are lower compared to higher frequencies. Dependent on the local regulations, the maximum allowed transmitted power in this band amounts to 36 dBm EIRP, which corresponds to a maximum available power of 27 μW at a distance of 10 m [21]. So the circuit design challenge is to build an RF to DC rectifier circuit with highest possible efficiency, in the best case of over 40%, where a threshold voltage compensation circuit can effectively maximize the efficiency and decrease the input sensitivity at the same time [36].
Another possibility to harvest energy from the environment is the integration of photo-voltaic (PV) power (solar) cells into a standard CMOS-process. Thus, by realizing the PV cell on chip, a single-IC solution for energy supply and application specific circuitry can be provided. A major advantage of this method is the decreased number of components involved in the overall system and the compact realization. In order to overcome the permanent dependence on ambient light, the harvested energy can be stored on a capacitor. Size and design of the solar cell determine the generated power on the chip.
PV solar cells can either be integrated by post-CMOS processing as shown in e.g. [22, 23], or directly into a standard CMOS technology as proposed in e.g. [14]. In comparison to standalone PV cells, which achieve an energy conversion factor around 24% [33], integrated standard-CMOS PV cells are limited to ≈2% efficiency [20, 30, 31]. The latter provide an output power of about 80 μW/mm2 at an illumination level of 25 klux (equivalent to a sunny, clear day in winter) and 1.4 μW/mm2 at 435 lux (equivalent to typical office illumination level).
3 Next generation wireless architectures
As presented in Sect. 1, the ever-increasing market penetration of smart-phones and mobile data usage rises to levels almost unthinkable a few years ago. In the following section the basics for the 5G wireless technologies and corresponding challenges for circuit design will be summarized.
3.1 LTE and 5G basics
From communications theory (Shannon’s law) follows a sufficient signal-to-noise ratio (SNR) in conjunction with the inherent use of higher-order modulation schemes, or a dramatically increased transmission bandwidth is needed to cope with raised data transmission rates. Thus, the third generation partnership project (3GPP) is currently enhancing the fourth generation long term evolution (LTE) framework by several staged releases over the next months, with recently releasing the 5G New Radio (NR) architecture [1]. LTE-Advanced in the 3GPP release 13 and beyond uses a multitude of often disjunctive frequency bands, higher-order modulation schemes like 256QAM, \(2\times 2\) or \(4\times 4\) multiple-input–multiple-output (MIMO), and link aggregation in time division duplex (TDD) and frequency-division duplex (FDD) modes. In 5G NR, LTE and its techniques will serve as anchor nodes to finally realize true multi-Gbps wireless data transmission rates.
Especially the frequency bands below 3 GHz are highly populated and fragmented due to the governmental licensing to several mobile operators within those bands. Consequently, to enlarge transmission bandwidth, LTE-Advanced defines three types of carrier (link) aggregation (CA) scenarios. As depicted for a simplified two channel aggregation concept in Fig. 4, there is a mode where neighboring carrier components (CC) – which are located within one frequency band – are combined to an intra-band contiguous mode, or non-neighboring channels form a non-contiguous CA channel. In LTE-Advanced, up to 5 channels in different frequency bands can be aggregated, each consisting of up 4 CC resulting in a maximum of 80 MHz bandwidth per channel. In contrast to backwards compatible LTE, 5G NR is also intended to flexibly utilize licensed and unlicensed bands up to millimeter wave (mm-wave) center frequencies. Additionally, the used bandwidths will rise up to 800 MHz or above.
Fig. 4.
Carrier Aggregation (CA) modes: (a) intra-band contiguous CA, (b) intra-band non-contiguous CA, and (c) inter-band CA
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From the perspective of the RF front-end and overall system design, especially the simultaneous transmission and reception of several aggregated large bandwidth channels introduces numerous challenges to wireless RF integrated transceivers. The use of multiple transmit (TX) or receive (RX) frequency bands in conjunction with up to \(8\times8\) MIMO antenna configurations increases the need for scaling of the structures within the integrated circuits for performance, power, and chip-size reasons. This inherently justifies the use of the smallest and thus most expensive technology nodes available (cf. Fig. 2). Nevertheless, also coupling effects and their obvious negative consequences are increasingly challenging, even if proper circuit design and layout techniques are used.
Like other wireless transmitters, also LTE-Advanced transmitters use distinct receive and transmit paths. Figure 5 depicts a simplified block diagram of such a multi-band integrated architecture utilizing two TX and two RX paths, but neglects further MIMO or auxiliary RX or TX paths. Nevertheless, still within this simplified block diagram, a general flexibility of configuration and adaption to different CA modes of operation is maintained. Of course, additional switches and multiplexers would be needed for true multi-band operation e.g. to configure the structure to operate in TDD mode using one PLL for TX and RX simultaneously keeping in mind that all these additional switching-paths can introduce additional unwanted coupling across the functional blocks. In contrast to Sect. 2.1, where there is a large spread of topologies and architectures, these high performance receivers and transmitters almost all utilize either zero- or low-IF topologies followed by high dynamic range (DR) analog-digital-converters (ADC) or digital-analog-converters (DAC) and extensive digital signal processing in the baseband (BB). These days, for example, mixed signal cancellation for carrier aggregation LTE receivers as the one depicted in Fig. 6 [28], use novel circuitry to sense for modulated interference and generate an interference cancellation signal in the digital domain to subsequently compensate for analog impairments and coupling effects which are generally often summarized as self-interference effects and corresponding mitigation techniques.
Fig. 5.
Simplified inter-band CA transceiver structure
Fig. 6.
Mixed signal CA LTE receiver architecture for the cancellation of modulated spurs [28]
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Figure 5 summarizes some of those effects. Besides classical self-interference problems, like TX-to-RX coupling due to limited amount of isolation in a duplexer filter in FDD mode, also local oscillator (LO) pulling by the TX power amplifier (PA) or PA non-linearities, TX harmonics, or oscillator phase noise, and a combination of all those in and in-between several components of the system will lead to a significant desensitization of the corresponding receive paths. Also non-ideal BB signals (non-orthogonality and IQ coupling), here summarized as BB coupling, degrade the error vector magnitude (EVM) and adjacent channel suppression. Of course, also LO coupling, which can also be harmonically related between multiple RX and TX bands in CA scenarios and corresponding phase noise must be considered. All these effects are consequently reducing the signal-to-noise or -interference ratio. As self-interference poses a critical issue in CA-enabled TRX, many researchers and companies are trying to resolve the coupling effects within the IC to enhance the performance of their implementations. Foremost, analog mitigation techniques like fully-differential symmetrical structures or on-chip isolation techniques are used. But, as the results are often insufficient in terms of performance for the large number band combinations and scenarios, further adaptive digital signal processing is used to compensate for those coupling effects [13, 35].
Currently, most of the manufacturers of mobile communication chip-sets realize their RF TRX designs in 40 nm [7], 28 nm [11, 12], or similar CMOS technologies.
Recently, the latest designs are fabricated in 16 nm or 14 nm Fin-FET CMOS [4, 17]. The corresponding advantages of low voltage operation as well as drastically increased transit frequency and integration density are utilized for the realization of novel circuit design concepts, e.g. in [4] where a specialized type of filter-less reconfigurable harmonic rejection mixer has been shown or [17] where a ultra-low power wide-band RX circuit for CA scenarios was demonstrated.
4 Conclusion
This paper summarizes the ongoing – often conflicting – approaches in state-of-the-art (SoA) integrated circuit design for communication systems. By weighing the factors IP development and production costs, integration level, energy efficiency, the potential production volume of a realized product, and driven by the needs of the corresponding applications, the designers of integrated circuits either select well-established cost efficient technologies as 180 nm CMOS or costly leading edge technologies like 14 nm FinFET for their designs. For both cases, industry as well as academia researchers face a widespread field of unexplored challenging topics for integrated circuit and system design.
Based on two examples of wireless transmission systems, we present our current research focus. On the one hand, we work on ultra-low power RF transceivers for IoT and health-care applications. Here we want to employ SoA mixed-signal circuit techniques for efficient signal generation and further enhance the sensitivity and interference immunity by adopting the technique of translational circuit techniques to the RF domain. On the other hand, due to the clear tendency to highest speed and lowest power wireless data transfer in 4G and 5G applications, RF integrated circuit designers face entirely new problem statements to be tackled using the most advanced technologies available. Due to impairments caused by the required massive parallelization in terms of multi-band and multi-antenna RF paths as well as signal bandwidths of multiples of 100 MHz, we work on novel circuit topologies in analog and digital domain to sense for non-idealities and coupling artifacts typical for such systems.
Acknowledgements
Open access funding provided by Johannes Kepler University Linz. The authors wish to acknowledge DMCE GmbH & Co KG, a subsidiary of Intel Corp., for supporting this work partly carried out at the Christian Doppler Laboratory for Digitally Assisted RF Transceivers for Future Mobile Communications. The financial support by the Austrian Federal Ministry of Science, Research and Economy and the National Foundation for Research, Technology and Development is gratefully acknowledged.
Open Access This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
